From patchwork Fri Feb 9 08:39:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shravan Kumar Ramani X-Patchwork-Id: 198783 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp711034dyd; Fri, 9 Feb 2024 00:42:03 -0800 (PST) X-Google-Smtp-Source: AGHT+IGykvVU7bIMODvre4XvmJUA3XaMlw1fzpfmecsJHE7ryeY/qEha2EKl94FKO3ztvhwGIHVH X-Received: by 2002:a05:6a21:9703:b0:19c:9ebc:93b1 with SMTP id ub3-20020a056a21970300b0019c9ebc93b1mr839483pzb.59.1707468123182; Fri, 09 Feb 2024 00:42:03 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUp3/BSzuHLWbTw/RxXEJPvXZZj9DU35vF+NzjJtvNXvL/QiC4HNJxaaa9DmtStU8I6AaMvNzSr8TvVAehfH3lv+kC78g== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [139.178.88.99]) by mx.google.com with ESMTPS id e63-20020a17090a6fc500b00296f79733d1si1246073pjk.115.2024.02.09.00.42.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Feb 2024 00:42:03 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-59119-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99; Authentication-Results: mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=oKannA62; arc=fail (signature failed); spf=pass (google.com: domain of linux-kernel+bounces-59119-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-59119-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id E57B3287365 for ; Fri, 9 Feb 2024 08:42:02 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0B7CE67C5D; Fri, 9 Feb 2024 08:40:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="oKannA62" Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2054.outbound.protection.outlook.com [40.107.223.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45B25664A2; Fri, 9 Feb 2024 08:40:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.223.54 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707468043; cv=fail; b=ghYlM6f86RGH6Aq89q08dFHqVTSU4qIYkTYDHBGQyn8yBLpO482y3fjV/rPOa0lT9rroER3hY5+Be7g8j4TdHK9dnoUGVhOKBp3522COkuxT6SQvxBpdXI9YJRUkiH/DPD6uVl4rWLaqevT1OimflS7WkCZDqYCU9QBNDEk4Lc8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707468043; c=relaxed/simple; bh=lOK1DwaZlHVX926/hU7fLkjHIgtZhm5gxIiTs2GlNq4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dMhsHLbUiy2C6G2IzrolV3yDCpgNPWvGpLnoP05fy5phPCCyQgw4wxvuGZPYkzkoZm8JEjXgszCPIkhX/ASxRrnz+aJaiDBZJ99SLT1XUAj2c60wqXNsO6DOJA/96n7v/Tje5xJ3haUZTY6CzPsZutFwFtq8xAqI664P1j9Q0Io= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=oKannA62; arc=fail smtp.client-ip=40.107.223.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=UN8CpQkn2ZjhJGpG/9fNoxflXJ2HbNUA/MwhlmHRvKg5KfndkaeXX0kkPoBOyJRghiHHtUYLnjEXuB0qUlSxQh6GrIoy3xTxV44ebkSdo6X+2mty+Ir00cCB8cjiMnnp54ViHDJHKpKWHxjC2jUfN9i0CYfIsFsLDbYTYxRc1J8VEQerBwNQ2UjKIgzn1u4+6qZx9pxPq2J9cm4O9G73vFPfkd/CNiz6pHW1ZqeMxZrf35/SKC1yZjq0IZRG0ZPzjpKQ+PNqapvCUDH4NxVpUD62fJwofKRTh6JblnrVM9/vrK3QUhXLLh5pdp8vn+jrt15OZvWK942xszUcG7aGZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=TDu3fl6DoOoIzRAZuGSuq/jUHs2oXp91UUbXPaWWQ4Q=; b=AoKE7SBYxSonbU/Vs8rkyNyjg0IC4yN6hRU51GIHl3oQthFyOhVjHZCBTBxly0Z5ksS9QyaotDqBVhM7imcFGcUgwW4avb3P7hqUO7x+BowyNYrZ/PMwncTCToE2mYS4U8ShP+9UB8IBUjZlvKSKoOkNIi2xFnbkPLANGFMmXvIqaH0p4QLoB43A0hTE4V4cJcx3fz7nK2bMB0QcB5y4TVCq8MZHZNZGISplD+IgkrOqxVmaQEXXB3hLBTSh76ZTTdCIz6zrnYnHTgCRNws8fvkpoLcbsIt7Q49fSp0dcBbLmmlhixvDTq/fPyws0tY4q/AdS3hRGNwW135qmOJPXA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=redhat.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=TDu3fl6DoOoIzRAZuGSuq/jUHs2oXp91UUbXPaWWQ4Q=; b=oKannA62YvsNqrTL3a+g0CNFcQPY3q1YkryL7fpkxfK6Qut3m290/29bij6ORlX36068FsnwHdHYXrdkYfQ/pzCFJszsm/AUwoVjMX0Lc9Y4cTUGbM9UB4RebQrh+LnpxNtK5ux2HrVeojnKF5sFk+4TdP17DOgXpK24pqOLPO7jsbNXoHe71yz/fdAQySqMio6lcoAmMvJ5Qf971XC7AUejTqyndIY6K9FFhSSO4KZtWhLg9nnhAaVGul/BuKD3Kvjhfg90s22zwabdpgBZrZf5UHZxC1dYTmoM2shlVPJiZvryNRMU7w3pWfCrsmdP/APj0piGB/a2hRAOnfZmLg== Received: from DM6PR03CA0098.namprd03.prod.outlook.com (2603:10b6:5:333::31) by CY8PR12MB8215.namprd12.prod.outlook.com (2603:10b6:930:77::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.13; Fri, 9 Feb 2024 08:40:37 +0000 Received: from SN1PEPF0002BA4B.namprd03.prod.outlook.com (2603:10b6:5:333:cafe::ef) by DM6PR03CA0098.outlook.office365.com (2603:10b6:5:333::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7249.39 via Frontend Transport; Fri, 9 Feb 2024 08:40:37 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by SN1PEPF0002BA4B.mail.protection.outlook.com (10.167.242.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7249.19 via Frontend Transport; Fri, 9 Feb 2024 08:40:36 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Fri, 9 Feb 2024 00:40:16 -0800 Received: from drhqmail202.nvidia.com (10.126.190.181) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 9 Feb 2024 00:40:15 -0800 Received: from vdi.nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 9 Feb 2024 00:40:15 -0800 From: Shravan Kumar Ramani To: Hans de Goede , Ilpo Jarvinen , Vadim Pasternak , "David Thompson" CC: Shravan Kumar Ramani , , Subject: [PATCH v2 3/4] platform/mellanox: mlxbf-pmc: Add support for 64-bit counters and cycle count Date: Fri, 9 Feb 2024 03:39:56 -0500 Message-ID: <737777a08e6decf3033334ad2d6e49c9f374e026.1707466888.git.shravankr@nvidia.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA4B:EE_|CY8PR12MB8215:EE_ X-MS-Office365-Filtering-Correlation-Id: 10008fda-7da4-4794-20de-08dc294ac9cb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jmRNJbP8fwlh0JO9mhD+Y9Ac0beXtDlp+CVonFLt0V6VTuXuebTVZ3LfGy++Rbu+yDTNz6dzQEFPtFyiY7aLLVDYwE42Z2MrOcQgl2bv+8NzDsfT8EqIhD1Q3LwL3wf5+Sqh7jVz163DlGGbJUYa26OAj/tV49l3P3Vv6MyMhPNJa8X7JigfLecctIM4E+RYr0FJlFpGRUTYjWBlXPl3xkWtv1DT439Evv76XhQjlWuJkdQ3OnoX1v1nes4+SEghYLwu6eHo6bCq87NqbxvsUhHzo1o2mIPkrUSOLFppRgGy4ecxzykwP0kHSwysm0uUFCogq790KAHSvbnXMeFR9V8XqBB0CRguky2N3IklWAcF9hj6flg1z3c9ujXKvBUES/AwSTcBWXKXD6uh2FxQIFtirimE7yRWUFZZUBjOTB8/ialtiOygWZcgsQPMnhqGvLtw8vu/mo2HSxCN4vxSz5kHXPr5MSacsk7r+J4MKvhrPoQzpoFMzsZ2OKrVu+mQ+KyDZtDapJZv19jNjUe9z7mzD1aH8iFMSjaAYJr6PF807xt24k2IzF7rKSKepzYMQ8/8VNrwwqLft73m/281s01rZZ/NuRvIh1PR4q/hPl8= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(376002)(136003)(39860400002)(346002)(396003)(230922051799003)(451199024)(186009)(82310400011)(1800799012)(64100799003)(46966006)(40470700004)(36840700001)(5660300002)(70206006)(4326008)(8676002)(70586007)(8936002)(2906002)(83380400001)(26005)(426003)(336012)(82740400003)(356005)(7636003)(36756003)(86362001)(110136005)(6636002)(54906003)(6666004)(316002)(41300700001)(2616005)(478600001)(7696005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Feb 2024 08:40:36.8212 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 10008fda-7da4-4794-20de-08dc294ac9cb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4B.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8215 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790410095200297359 X-GMAIL-MSGID: 1790410095200297359 Add support for programming any counter to monitor the cycle count. Since counting of cycles using 32-bit ocunters would result in frequent wraparounds, add the ability to combine 2 adjacent 32-bit counters to form 1 64-bit counter. Both these features are supported by BlueField-3 PMC hardware, hence the required bit-fields are exposed by the driver via sysfs to allow the user to configure as needed. Signed-off-by: Shravan Kumar Ramani Reviewed-by: David Thompson Reviewed-by: Vadim Pasternak --- drivers/platform/mellanox/mlxbf-pmc.c | 134 ++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/drivers/platform/mellanox/mlxbf-pmc.c b/drivers/platform/mellanox/mlxbf-pmc.c index e3f1ae772e43..1b9356a3ffab 100644 --- a/drivers/platform/mellanox/mlxbf-pmc.c +++ b/drivers/platform/mellanox/mlxbf-pmc.c @@ -88,6 +88,8 @@ #define MLXBF_PMC_CRSPACE_PERFMON_CTL(n) (n * MLXBF_PMC_CRSPACE_PERFMON_REG0_SZ) #define MLXBF_PMC_CRSPACE_PERFMON_EN BIT(30) #define MLXBF_PMC_CRSPACE_PERFMON_CLR BIT(28) +#define MLXBF_PMC_CRSPACE_PERFMON_UOC GENMASK(15, 0) +#define MLXBF_PMC_CRSPACE_PERFMON_COUNT_CLOCK(n) (MLXBF_PMC_CRSPACE_PERFMON_CTL(n) + 0x4) #define MLXBF_PMC_CRSPACE_PERFMON_VAL0(n) (MLXBF_PMC_CRSPACE_PERFMON_CTL(n) + 0xc) /** @@ -114,6 +116,8 @@ struct mlxbf_pmc_attribute { * @attr_event: Attributes for "event" sysfs files * @attr_event_list: Attributes for "event_list" sysfs files * @attr_enable: Attributes for "enable" sysfs files + * @attr_use_odd_counter: Attributes for "use_odd_counter" sysfs files + * @attr_count_clock: Attributes for "count_clock" sysfs files * @block_attr: All attributes needed for the block * @block_attr_grp: Attribute group for the block */ @@ -126,6 +130,8 @@ struct mlxbf_pmc_block_info { struct mlxbf_pmc_attribute *attr_event; struct mlxbf_pmc_attribute attr_event_list; struct mlxbf_pmc_attribute attr_enable; + struct mlxbf_pmc_attribute attr_use_odd_counter; + struct mlxbf_pmc_attribute attr_count_clock; struct attribute *block_attr[MLXBF_PMC_MAX_ATTRS]; struct attribute_group block_attr_grp; }; @@ -1761,6 +1767,103 @@ static ssize_t mlxbf_pmc_enable_store(struct device *dev, return count; } +/* Show function for "use_odd_counter" sysfs files - only for crspace */ +static ssize_t mlxbf_pmc_use_odd_counter_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mlxbf_pmc_attribute *attr_use_odd_counter = container_of( + attr, struct mlxbf_pmc_attribute, dev_attr); + unsigned int blk_num; + u32 value, reg; + + blk_num = attr_use_odd_counter->nr; + + if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + + MLXBF_PMC_CRSPACE_PERFMON_CTL(pmc->block[blk_num].counters), + ®)) + return -EINVAL; + + value = FIELD_GET(MLXBF_PMC_CRSPACE_PERFMON_UOC, reg); + + return sysfs_emit(buf, "%u\n", value); +} + +/* Store function for "use_odd_counter" sysfs files - only for crspace */ +static ssize_t mlxbf_pmc_use_odd_counter_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct mlxbf_pmc_attribute *attr_use_odd_counter = container_of( + attr, struct mlxbf_pmc_attribute, dev_attr); + unsigned int blk_num; + u32 uoc, reg; + int err; + + blk_num = attr_use_odd_counter->nr; + + err = kstrtouint(buf, 0, &uoc); + if (err < 0) + return err; + + err = mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + + MLXBF_PMC_CRSPACE_PERFMON_CTL(pmc->block[blk_num].counters), + ®); + if (err) + return -EINVAL; + + reg &= ~MLXBF_PMC_CRSPACE_PERFMON_UOC; + reg |= FIELD_PREP(MLXBF_PMC_CRSPACE_PERFMON_UOC, uoc); + + mlxbf_pmc_write(pmc->block[blk_num].mmio_base + + MLXBF_PMC_CRSPACE_PERFMON_CTL(pmc->block[blk_num].counters), + MLXBF_PMC_WRITE_REG_32, reg); + + return count; +} + +/* Show function for "count_clock" sysfs files - only for crspace */ +static ssize_t mlxbf_pmc_count_clock_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mlxbf_pmc_attribute *attr_count_clock = container_of( + attr, struct mlxbf_pmc_attribute, dev_attr); + unsigned int blk_num; + u32 reg; + + blk_num = attr_count_clock->nr; + + if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + + MLXBF_PMC_CRSPACE_PERFMON_COUNT_CLOCK(pmc->block[blk_num].counters), + ®)) + return -EINVAL; + + return sysfs_emit(buf, "%u\n", reg); +} + +/* Store function for "count_clock" sysfs files - only for crspace */ +static ssize_t mlxbf_pmc_count_clock_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct mlxbf_pmc_attribute *attr_count_clock = container_of( + attr, struct mlxbf_pmc_attribute, dev_attr); + unsigned int blk_num; + u32 reg; + int err; + + blk_num = attr_count_clock->nr; + + err = kstrtouint(buf, 0, ®); + if (err < 0) + return err; + + mlxbf_pmc_write(pmc->block[blk_num].mmio_base + + MLXBF_PMC_CRSPACE_PERFMON_COUNT_CLOCK(pmc->block[blk_num].counters), + MLXBF_PMC_WRITE_REG_32, reg); + + return count; +} + /* Populate attributes for blocks with counters to monitor performance */ static int mlxbf_pmc_init_perftype_counter(struct device *dev, unsigned int blk_num) { @@ -1794,6 +1897,37 @@ static int mlxbf_pmc_init_perftype_counter(struct device *dev, unsigned int blk_ attr = NULL; } + if (pmc->block[blk_num].type == MLXBF_PMC_TYPE_CRSPACE) { + /* + * Couple adjacent odd and even 32-bit counters to form 64-bit counters + * using "use_odd_counter" sysfs which has one bit per even counter. + */ + attr = &pmc->block[blk_num].attr_use_odd_counter; + attr->dev_attr.attr.mode = 0644; + attr->dev_attr.show = mlxbf_pmc_use_odd_counter_show; + attr->dev_attr.store = mlxbf_pmc_use_odd_counter_store; + attr->nr = blk_num; + attr->dev_attr.attr.name = devm_kasprintf(dev, GFP_KERNEL, + "use_odd_counter"); + if (!attr->dev_attr.attr.name) + return -ENOMEM; + pmc->block[blk_num].block_attr[++i] = &attr->dev_attr.attr; + attr = NULL; + + /* Program crspace counters to count clock cycles using "count_clock" sysfs */ + attr = &pmc->block[blk_num].attr_count_clock; + attr->dev_attr.attr.mode = 0644; + attr->dev_attr.show = mlxbf_pmc_count_clock_show; + attr->dev_attr.store = mlxbf_pmc_count_clock_store; + attr->nr = blk_num; + attr->dev_attr.attr.name = devm_kasprintf(dev, GFP_KERNEL, + "count_clock"); + if (!attr->dev_attr.attr.name) + return -ENOMEM; + pmc->block[blk_num].block_attr[++i] = &attr->dev_attr.attr; + attr = NULL; + } + pmc->block[blk_num].attr_counter = devm_kcalloc( dev, pmc->block[blk_num].counters, sizeof(struct mlxbf_pmc_attribute), GFP_KERNEL);