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Fri, 9 Dec 2022 07:54:50 -0600 From: Michal Simek To: , , , CC: Piyush Mehta , David Heidelberg , Greg Kroah-Hartman , Krzysztof Kozlowski , Michael Tretter , Rob Herring , Robert Hancock , , Subject: [PATCH] arm64: dts: zynqmp: Add mode-pin GPIO controller DT node Date: Fri, 9 Dec 2022 14:54:47 +0100 Message-ID: <69924a8e2c01e5a1d25d098adc53224ddb841f46.1670594085.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT100:EE_|SA1PR12MB7412:EE_ X-MS-Office365-Filtering-Correlation-Id: 01468f1d-b2bb-4621-8351-08dad9ecf1ea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: m09LUeWabY0ppKXoy/Kbd5Zs6b6PoX1aUr7NyMNozl5VFMjvJDJY+KcVunMmdFcI9g41BFMW7T9B5tBt8GH4+xpYeXihVh0jqv92swhtn6Zxo+Co7O6hR0on4T3uNLwqBUodtXvip91A4Xg+ErtZ9wXN2KoyW3P3Fk+nGH+o8byb/WTHrQr8VbaFz02/WG83+esHeX4S+9Gzv8yZJtngL6AFDSIIFq+rvis9ONA3BNFjhlmKKjFgqp/y3sJTcM4tjHFG8rldBxjyYbGdHZ+49zfw5cxnFHbwOc9UiW4XiSGPZyJ6KXiR+gBsY4R+unqudiG1iqd/LcjgYczsVPbdECULbItlM0rkzxnIt6MP+msnuk2uINbRopm23dlFYN6821yhWOaSRh+jMqUikRyWU/Ok4I/B7cqT5ssDk48GhOmotRWHZfbQFUmsNtCXMmhJlIpn+FzGF6IQy4cCg83mSADkG5eMlg+7JGfxgBSkHgMJNDX0Uqp0eGFwTMk5oEXup0CI67hIwTc+VMF/UAW9EbZJDYEMY16N0INURlar3mxu6P86nIMf0Ij80Q8Y9DueFtytTNMbD95PJko169UzbR6zQ9oun42xmvnjJ113kxHq7/QGbc2LjEzPwG4ZX7iW5NblnE4xDzjWSYVy7Dx7W478S2o/oEtfJPvyC809qQIRhqKnBIgnPyjvJrsmJxGTuBubAlAmQv5tpZHpLYeGuiLA34Nik6Eyod6lsY8W8xv1697Ja8IG1nmOhe46KaRi X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(39860400002)(376002)(346002)(396003)(451199015)(46966006)(36840700001)(40470700004)(478600001)(6666004)(4326008)(8676002)(2616005)(36860700001)(36756003)(316002)(356005)(82310400005)(54906003)(26005)(186003)(40460700003)(82740400003)(110136005)(70206006)(70586007)(86362001)(81166007)(83380400001)(40480700001)(2906002)(336012)(44832011)(8936002)(16526019)(5660300002)(426003)(47076005)(7416002)(41300700001)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2022 13:54:51.9752 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 01468f1d-b2bb-4621-8351-08dad9ecf1ea X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT100.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7412 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1751745579251883493?= X-GMAIL-MSGID: =?utf-8?q?1751745579251883493?= From: Piyush Mehta Add mode-pin GPIO controller DT node in zynqmp.dtsi and wire it to usb0 controller. All Xilinx evaluation boards are using modepin gpio for ULPI reset that's why wire it directly in zynqmp instead of c&p the same line to every board specific file. Signed-off-by: Piyush Mehta Signed-off-by: Michal Simek Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 99273cbbc75f..8553299f12eb 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -13,6 +13,7 @@ */ #include +#include #include #include @@ -183,6 +184,12 @@ pinctrl0: pinctrl { compatible = "xlnx,zynqmp-pinctrl"; status = "disabled"; }; + + modepin_gpio: gpio { + compatible = "xlnx,zynqmp-gpio-modepin"; + gpio-controller; + #gpio-cells = <2>; + }; }; }; @@ -814,6 +821,7 @@ usb0: usb@ff9d0000 { <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; + reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; ranges; dwc3_0: usb@fe200000 {