Message ID | 69924a8e2c01e5a1d25d098adc53224ddb841f46.1670594085.git.michal.simek@amd.com |
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Fri, 9 Dec 2022 07:54:50 -0600 From: Michal Simek <michal.simek@amd.com> To: <linux-kernel@vger.kernel.org>, <monstr@monstr.eu>, <michal.simek@xilinx.com>, <git@xilinx.com> CC: Piyush Mehta <piyush.mehta@xilinx.com>, David Heidelberg <david@ixit.cz>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Michael Tretter <m.tretter@pengutronix.de>, Rob Herring <robh+dt@kernel.org>, Robert Hancock <robert.hancock@calian.com>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org> Subject: [PATCH] arm64: dts: zynqmp: Add mode-pin GPIO controller DT node Date: Fri, 9 Dec 2022 14:54:47 +0100 Message-ID: <69924a8e2c01e5a1d25d098adc53224ddb841f46.1670594085.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT100:EE_|SA1PR12MB7412:EE_ X-MS-Office365-Filtering-Correlation-Id: 01468f1d-b2bb-4621-8351-08dad9ecf1ea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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arm64: dts: zynqmp: Add mode-pin GPIO controller DT node
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Commit Message
Michal Simek
Dec. 9, 2022, 1:54 p.m. UTC
From: Piyush Mehta <piyush.mehta@xilinx.com> Add mode-pin GPIO controller DT node in zynqmp.dtsi and wire it to usb0 controller. All Xilinx evaluation boards are using modepin gpio for ULPI reset that's why wire it directly in zynqmp instead of c&p the same line to every board specific file. Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)
Comments
On 12/9/22 14:54, Michal Simek wrote: > From: Piyush Mehta <piyush.mehta@xilinx.com> > > Add mode-pin GPIO controller DT node in zynqmp.dtsi and wire it to usb0 > controller. All Xilinx evaluation boards are using modepin gpio for ULPI > reset that's why wire it directly in zynqmp instead of c&p the same line to > every board specific file. > > Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com> > Signed-off-by: Michal Simek <michal.simek@xilinx.com> > Signed-off-by: Michal Simek <michal.simek@amd.com> > --- > > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > index 99273cbbc75f..8553299f12eb 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > @@ -13,6 +13,7 @@ > */ > > #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> > +#include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/power/xlnx-zynqmp-power.h> > #include <dt-bindings/reset/xlnx-zynqmp-resets.h> > > @@ -183,6 +184,12 @@ pinctrl0: pinctrl { > compatible = "xlnx,zynqmp-pinctrl"; > status = "disabled"; > }; > + > + modepin_gpio: gpio { > + compatible = "xlnx,zynqmp-gpio-modepin"; > + gpio-controller; > + #gpio-cells = <2>; > + }; > }; > }; > > @@ -814,6 +821,7 @@ usb0: usb@ff9d0000 { > <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, > <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; > reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; > + reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; > ranges; > > dwc3_0: usb@fe200000 { Applied. M
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 99273cbbc75f..8553299f12eb 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -13,6 +13,7 @@ */ #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/power/xlnx-zynqmp-power.h> #include <dt-bindings/reset/xlnx-zynqmp-resets.h> @@ -183,6 +184,12 @@ pinctrl0: pinctrl { compatible = "xlnx,zynqmp-pinctrl"; status = "disabled"; }; + + modepin_gpio: gpio { + compatible = "xlnx,zynqmp-gpio-modepin"; + gpio-controller; + #gpio-cells = <2>; + }; }; }; @@ -814,6 +821,7 @@ usb0: usb@ff9d0000 { <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; + reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; ranges; dwc3_0: usb@fe200000 {