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Sat, 4 Nov 2023 20:51:27 +0000 Date: Sat, 4 Nov 2023 13:51:23 -0700 From: Dan Williams To: CC: , , , Subject: [GIT PULL] Compute Express Link (CXL) for 6.7 Message-ID: <6546aecbae94b_3f602948@dwillia2-mobl3.amr.corp.intel.com.notmuch> Content-Disposition: inline X-ClientProxiedBy: MW4PR04CA0195.namprd04.prod.outlook.com (2603:10b6:303:86::20) To PH8PR11MB8107.namprd11.prod.outlook.com (2603:10b6:510:256::6) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8107:EE_|PH0PR11MB7544:EE_ X-MS-Office365-Filtering-Correlation-Id: edad1677-e57c-4125-abdc-08dbdd77cfb7 X-LD-Processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: eBXihz651vM0s+xSfLtYYnTjCBN3OCaK42nXedW3CEmmvR6e558zCWjzsl0T3zQrZU0vHFTAv0/5O4lRbHAm8D82fEX1/z3F7EK1NLlwazYnskY/ssmDjgANN2/Xo4lwK47AlUQwc7XY+93eFi/Hd9E/M16Y+EgjA+QcTPTtwyUV8VQXoRz26fln9D/X1yzSiZ0is3hLKlx0m3OKP9W+Q7uBs7fo6kB29mMfRhJ77Fb61MeMGbZKXyM9VGaZlKMV6BMUnT7iPsq4w42GhHqUGff9zk5IC1/jsXm0UmqHMiHu+qxpdEdZdW15NbNApc+b2rUnWBSE6/U/Z2dumSiLzGlioYF4ZXL+YckEiVpmgGaCNpxQOgwlbAtySVTrILDyFpZiNnLjKau/F93DfgZqSCDqD0DV/xdDVurNulNTSx5eGOCtY28TlaYXMlGDCIFD57KLhr4UAATWWDWgAUIu049klUx8S5c6e6x/jM87uHWK9dAX3K2ikJEjoe2FIgIuErF2k4Ny+C5VwJzN8NkRQypCtJ0mdZH6T7VjAsUnDEBaihWNjSO4HDCvu/GPES53vELs1hWI2BadLzRLNYLw5J/nuuWas9xvSs9PMRiHhql8x6P9dfGrTGvXCgd6bcsQ X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PH8PR11MB8107.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(376002)(346002)(39860400002)(366004)(396003)(136003)(230922051799003)(230173577357003)(230273577357003)(64100799003)(451199024)(186009)(1800799009)(9686003)(6512007)(26005)(6666004)(478600001)(6506007)(2906002)(8676002)(83380400001)(316002)(5660300002)(66946007)(41300700001)(66556008)(8936002)(66476007)(4326008)(6486002)(6916009)(38100700002)(82960400001)(86362001);DIR:OUT;SFP:1102; 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Sat, 04 Nov 2023 13:51:50 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781668106548674922 X-GMAIL-MSGID: 1781668106548674922 Hi Linus, please pull from: git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl tags/cxl-for-6.7 ...to receive the CXL update for this cycle. The main new functionality this time is work to allow Linux to natively handle CXL link protocol errors signalled via PCIe AER for current generation CXL platforms. This required some enlightenment of the PCIe AER core to workaround the fact that current generation RCH (Restricted CXL Host) platforms physically hide topology details and registers via a mechanism called RCRB (Root Complex Register Block). It has a minor conflict with the PCI updates you have already pulled this cycle, sample resolution below. The next major highlight is reworks to address bugs in parsing region configurations for next generation VH (Virtual Host) topologies. The old broken algorithm is replaced with a simpler one that significantly increases the number of region configurations supported by Linux. This is again relevant for error handling so that forward and reverse address translation of memory errors can be carried out by Linux for memory regions instantiated by platform firmware. As for other cross-tree work, the ACPI table parsing code has been refactored for reuse parsing the "CDAT" structure which is an ACPI-like data structure that is reported by CXL devices. That work is in preparation for v6.8 support for CXL QoS. Think of this as dynamic generation of NUMA node topology information generated by Linux rather than platform firmware. Lastly, a number of internal object lifetime issues have been resolved along with misc. fixes and feature updates (decoders_committed sysfs ABI). This has all appeared in -next with a few late breaking fixes applied for reported issues, but otherwise no new reports since this past Monday. The touches of PCI and ACPI have received acks from Bjorn and Rafael respectively. --- Proposed merge resolution: +++ b/drivers/pci/pcie/aer.c @@@ -997,16 -1142,7 +1143,16 @@@ static void aer_recover_work_func(struc PCI_SLOT(entry.devfn), PCI_FUNC(entry.devfn)); continue; } - cper_print_aer(pdev, entry.severity, entry.regs); + pci_print_aer(pdev, entry.severity, entry.regs); + /* + * Memory for aer_capability_regs(entry.regs) is being allocated from the + * ghes_estatus_pool to protect it from overwriting when multiple sections + * are present in the error status. Thus free the same after processing + * the data. + */ + ghes_estatus_pool_region_free((unsigned long)entry.regs, + sizeof(struct aer_capability_regs)); + if (entry.severity == AER_NONFATAL) pcie_do_recovery(pdev, pci_channel_io_normal, aer_root_reset); --- The following changes since commit 178e1ea6a68f12967ee0e9afc4d79a2939acd43c: ACPICA: Add defines for CDAT SSLBIS (2023-10-03 16:04:22 +0200) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl tags/cxl-for-6.7 for you to fetch changes up to 4b92894064b3df472b2cf5741c7f080e16dcd1ec: lib/fw_table: Remove acpi_parse_entries_array() export (2023-11-02 15:17:21 -0700) ---------------------------------------------------------------- cxl for v6.7 - Add support for RCH (Restricted CXL Host) Error recovery - Fix several region assembly bugs - Fix mem-device lifetime issues relative to the sanitize command and RCH topology. - Refactor ACPI table parsing for CDAT parsing re-use in preparation for CXL QOS support. ---------------------------------------------------------------- Alison Schofield (4): cxl/mbox: Remove useless cast in cxl_mem_create_range_info() cxl/region: Prepare the decoder match range helper for reuse cxl/region: Calculate a target position in a region interleave cxl/region: Use cxl_calc_interleave_pos() for auto-discovery Dan Carpenter (1): cxl/hdm: Fix && vs || bug Dan Williams (19): cxl/port: Quiet warning messages from the cxl_test environment cxl/pci: Remove unnecessary device reference management in sanitize work cxl/pci: Cleanup 'sanitize' to always poll cxl/pci: Remove hardirq handler for cxl_request_irq() cxl/pci: Remove inconsistent usage of dev_err_probe() cxl/pci: Clarify devm host for memdev relative setup cxl/pci: Fix sanitize notifier setup cxl/memdev: Fix sanitize vs decoder setup locking cxl/mem: Fix shutdown order tools/testing/cxl: Make cxl_memdev_state available to other command emulation tools/testing/cxl: Add 'sanitize notifier' support cxl/port: Fix delete_endpoint() vs parent unregistration race cxl/port: Fix @host confusion in cxl_dport_setup_regs() Merge branch 'for-6.7/cxl-rch-eh' into cxl/next Merge branch 'for-6.7/cxl-qtg' into cxl/next Merge branch 'for-6.7/cxl' into cxl/next Merge branch 'for-6.7/cxl-commited' into cxl/next cxl/hdm: Remove broken error path lib/fw_table: Remove acpi_parse_entries_array() export Dave Jiang (6): cxl: Add cxl_decoders_committed() helper cxl: Add decoders_committed sysfs attribute to cxl_port cxl: Export QTG ids from CFMWS to sysfs as qos_class attribute cxl: Add checksum verification to CDAT from CXL cxl: Add support for reading CXL switch CDAT table acpi: Move common tables helper functions to common lib Ira Weiny (1): cxl/pci: Update comment Jim Harris (2): cxl/region: Do not try to cleanup after cxl_region_setup_targets() fails cxl/region: Fix x1 root-decoder granularity calculations Li Zhijian (1): cxl/region: Fix cxl_region_rwsem lock held when returning to user space Robert Richter (12): cxl/core/regs: Rename @dev to @host in struct cxl_register_map cxl/port: Rename @comp_map to @reg_map in struct cxl_register_map cxl/port: Pre-initialize component register mappings cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state cxl/hdm: Use stored Component Register mappings to map HDM decoder capability cxl/pci: Remove Component Register base address from struct cxl_dev_state cxl/port: Remove Component Register base address from struct cxl_port cxl/pci: Add RCH downstream port AER register discovery PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling cxl/core/regs: Rename phys_addr in cxl_map_component_regs() cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devm Terry Bowman (6): PCI/AER: Refactor cper_print_aer() for use by CXL driver module cxl/pci: Update CXL error logging to use RAS register address cxl/pci: Map RCH downstream AER registers for logging protocol errors cxl/pci: Add RCH downstream port error logging cxl/pci: Disable root port interrupts in RCH mode cxl/pci: Change CXL AER support check to use native AER Vishal Verma (2): MAINTAINERS: Add tools/testing/cxl files to CXL tools/testing/cxl: Slow down the mock firmware transfer Documentation/ABI/testing/sysfs-bus-cxl | 30 ++++ MAINTAINERS | 3 + drivers/acpi/Kconfig | 1 + drivers/acpi/tables.c | 173 -------------------- drivers/cxl/acpi.c | 3 + drivers/cxl/core/core.h | 2 + drivers/cxl/core/hdm.c | 93 +++++------ drivers/cxl/core/mbox.c | 60 +++++-- drivers/cxl/core/memdev.c | 161 +++++++++---------- drivers/cxl/core/pci.c | 275 +++++++++++++++++++++++++++++--- drivers/cxl/core/port.c | 184 +++++++++++++++------ drivers/cxl/core/region.c | 266 +++++++++++++++++------------- drivers/cxl/core/regs.c | 73 ++++++--- drivers/cxl/cxl.h | 38 +++-- drivers/cxl/cxlmem.h | 17 +- drivers/cxl/mem.c | 7 +- drivers/cxl/pci.c | 107 ++++++------- drivers/cxl/port.c | 3 + drivers/pci/pcie/Kconfig | 9 ++ drivers/pci/pcie/aer.c | 159 +++++++++++++++++- include/linux/acpi.h | 42 ++--- include/linux/aer.h | 2 +- include/linux/fw_table.h | 43 +++++ lib/Kconfig | 3 + lib/Makefile | 2 + lib/fw_table.c | 188 ++++++++++++++++++++++ tools/testing/cxl/test/cxl.c | 2 +- tools/testing/cxl/test/mem.c | 83 ++++++++-- 28 files changed, 1375 insertions(+), 654 deletions(-) create mode 100644 include/linux/fw_table.h create mode 100644 lib/fw_table.c diff --cc drivers/pci/pcie/aer.c index dcd35993004e,41076cb2956e..42a3bd35a3e1 --- a/drivers/pci/pcie/aer.c