From patchwork Sun Oct 30 06:23:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 12901 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1666769wru; Sat, 29 Oct 2022 23:31:18 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5lGVEHyQ+oSfuSRaelPojjEOqBD5g3sEPZyzAd7zX9c4Y/JlaZ4nglXkpzoB7Udc+t0QUx X-Received: by 2002:a17:907:94ce:b0:79c:d3c5:e9f6 with SMTP id dn14-20020a17090794ce00b0079cd3c5e9f6mr6741947ejc.219.1667111478068; Sat, 29 Oct 2022 23:31:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667111478; cv=none; d=google.com; s=arc-20160816; b=en5AUpf2NZTYY3viy+fYIxkW0Df/olncZTuQ60XqP3THMKNYhZuFFGi4ceRxIfEKj8 BDLynQCBUYmP5ONUq+LvMnyFBumSsL7jQW1Nv12ltWtkSwj1IxumsI+9qTIWawdDCILi UIuYgCYdfXH9l1gL/X+dGT3K/II4HcNNphike+RATKOObE9sCZs3yOgJ5dJq29kv2Rno LsXo6lzM8MGh0O0ShMCa85SMjG5ZVhgIZXvExP3vQId3ecY5Owp5S1pfZwKBkkTfA3xd vb8HinR3Dpij03UJFRfVP7JW8M5lbwD0I6yg7E54BlB4nwVu/ZAcDCSb4j18ThRWxOI3 ja2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=LXJ25Yea3XCVp5p6VJZLMOh/U7NY2gTK0V6699ncLiU=; b=V2/rDKs9QcGEKdlzwNatxaT8PvcjwVgYLuxz7N5a61pp3Fv/7tGQwgQCcB1B/1btdx A9qC6UTJRbCZoVA0zg1uXEoI4OKqBJwldYAXd/ENekyFh4241nbILogXH74HncpcF7km coUS8HlRbyVBDbrPzHWXirhlaof3JBvdNt2Rp2Atxh0lz6/rCzK5mUwh4L6dM2ezfqh+ j7SClAfvyEu75wRIIepjrhvEIzE7Br2e3QTyKO38MAmvsLUizgHgOKngE9JhawpjgFMF zkRe7mgt+46Jy6GT4GsoZtgR1djqDkRadyJ9Z4AnFUw7C/s8OL9DzCO6FeiZSjnPrpSc yCXg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=MvxW5cuR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id qk7-20020a1709077f8700b0077fc66b581esi3941282ejc.688.2022.10.29.23.30.52; Sat, 29 Oct 2022 23:31:18 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=MvxW5cuR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231307AbiJ3GaU (ORCPT + 99 others); Sun, 30 Oct 2022 02:30:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54088 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230493AbiJ3G2J (ORCPT ); Sun, 30 Oct 2022 02:28:09 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3FFA72EE; Sat, 29 Oct 2022 23:24:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667111077; x=1698647077; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bxQogyGeF26Y2rtQ1vDn3KVS8MkMlSfBtAXMo5C8hPA=; b=MvxW5cuR8ecq7ysLL87E8Rjg0DHhKDzXpgFAV25UldEYGDi1q+VUkZ/a fpTBd+kIrBF79nMiHcb9LP6nZq8uc5LgFYASoM1skdhwCrDVivBxHqQ84 cVCGTjwwWclMPKc+Uk/2MuclSipmUzg7wGlwmBIDVRPV0qiZSrDu+z5t2 e+rYCVuRwOs/9KviERptFuRw3YPm7Nsgo6CqG7NJAlc9AG2wdPKvKk6DO EqIC0lAOWSqWeDgaRpQAwtEFlMTpdboavr/K17wawsgwb4on2dhid7eoi IwIGV6htovy9kZ9Qc/Y/HflTbhNJy1ueiyLrXFUH+escQT0QIY+pN2oK5 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10515"; a="395037187" X-IronPort-AV: E=Sophos;i="5.95,225,1661842800"; d="scan'208";a="395037187" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Oct 2022 23:24:09 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10515"; a="878393083" X-IronPort-AV: E=Sophos;i="5.95,225,1661842800"; d="scan'208";a="878393083" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Oct 2022 23:24:09 -0700 From: isaku.yamahata@intel.com To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, Paolo Bonzini , erdemaktas@google.com, Sean Christopherson , Sagi Shahar , David Matlack Subject: [PATCH v10 074/108] KVM: TDX: complete interrupts after tdexit Date: Sat, 29 Oct 2022 23:23:15 -0700 Message-Id: <62b2229edec27f04f0f0a7dbc1ff1fd1b1e13378.1667110240.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748093085003336111?= X-GMAIL-MSGID: =?utf-8?q?1748093085003336111?= From: Isaku Yamahata This corresponds to VMX __vmx_complete_interrupts(). Because TDX virtualize vAPIC, KVM only needs to care NMI injection. Signed-off-by: Isaku Yamahata Reviewed-by: Paolo Bonzini --- arch/x86/kvm/vmx/tdx.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c index f35ccf2b502d..af13c19af339 100644 --- a/arch/x86/kvm/vmx/tdx.c +++ b/arch/x86/kvm/vmx/tdx.c @@ -456,6 +456,14 @@ void tdx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) vcpu->kvm->vm_bugged = true; } +static void tdx_complete_interrupts(struct kvm_vcpu *vcpu) +{ + /* Avoid costly SEAMCALL if no nmi was injected */ + if (vcpu->arch.nmi_injected) + vcpu->arch.nmi_injected = td_management_read8(to_tdx(vcpu), + TD_VCPU_PEND_NMI); +} + struct tdx_uret_msr { u32 msr; unsigned int slot; @@ -524,6 +532,8 @@ fastpath_t tdx_vcpu_run(struct kvm_vcpu *vcpu) vcpu->arch.regs_avail &= ~VMX_REGS_LAZY_LOAD_SET; trace_kvm_exit(vcpu, KVM_ISA_VMX); + tdx_complete_interrupts(vcpu); + return EXIT_FASTPATH_NONE; }