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[2620:137:e000::1:20]) by mx.google.com with ESMTP id mp2-20020a17090b190200b00262bf80dc74si3415892pjb.77.2023.06.25.07.54.52; Sun, 25 Jun 2023 07:55:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=LA7zpzp7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230052AbjFYORq (ORCPT + 99 others); Sun, 25 Jun 2023 10:17:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230019AbjFYORp (ORCPT ); Sun, 25 Jun 2023 10:17:45 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E75EA1B1 for ; Sun, 25 Jun 2023 07:17:43 -0700 (PDT) Received: from sobremesa.fritz.box (unknown [IPv6:2a02:8010:65b5:0:bbb0:f8ec:7bc9:dbe4]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: alarumbe) by madras.collabora.co.uk (Postfix) with ESMTPSA id 05121660712A; Sun, 25 Jun 2023 15:17:42 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1687702662; bh=c6A/z4v0Vb7BYDRLc/MAHkq406/oHg3kcxtWC9wdQ3s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LA7zpzp7vJYS0LTXXxzIiZ56k4vnlFfWuoYSJ2RPVZaY6exE91MztSG+76C9URTA2 Gj/jLwEuyt948mFnJ8ifaAvTJMgEvJthuD+PWQxeyf2ehEp0G2v2MC2AzaiKisYbG2 txDIi8Qt4Bg904IDo6AUL09+o7QcmpdHxZv48alBIsaB+5OVoVB8/zzULofDo1q4Ps z7fnDACgjbyhzWWih4gBFldy+JTK+pAue4LqqHWAxqOHJXXLDsroDtY21Oli/qYIMo 5AxYLE/Pf4JN5X8SzlsRJ9E3Pjl8hkeuEb3tJfuYKomBeKr4aa421Dcb8rDqCex2nR bj4X41V0IDhwQ== From: =?utf-8?q?Adri=C3=A1n_Larumbe?= To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: =?utf-8?q?Adri=C3=A1n_Larumbe?= , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 1/3] drm/bridge: dw-hdmi: change YUV420 selection logic at clock setup Date: Sun, 25 Jun 2023 15:17:15 +0100 Message-Id: <6230bfae2cd97cf6527fc62ba5c850464919ccf8.1687702042.git.adrian.larumbe@collabora.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1769686859083520776?= X-GMAIL-MSGID: =?utf-8?q?1769686859083520776?= Right now clocking value selection code is prioritising RGB, YUV444 modes over YUV420 for HDMI2 sinks. However, because of the bus format selection procedure in dw-hdmi, for HDMI2 sinks YUV420 is the format that will always be picked during the drm bridge chain check stage. Later on dw_hdmi_setup will configure a colour space based on the bus format that doesn't match the pixel value we had calculated as described above. Fix it by bringing back dw-hdmi bus format check when picking the right pixel clock. Signed-off-by: Adrián Larumbe Acked-by: Neil Armstrong --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 6 ++++++ drivers/gpu/drm/meson/meson_dw_hdmi.c | 4 ++-- include/drm/bridge/dw_hdmi.h | 2 ++ 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index 3b40e0fdca5c..e6a456b72610 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -3346,6 +3346,12 @@ static int dw_hdmi_parse_dt(struct dw_hdmi *hdmi) return 0; } +bool dw_hdmi_bus_fmt_is_420(struct dw_hdmi *hdmi) +{ + return hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format); +} +EXPORT_SYMBOL_GPL(dw_hdmi_bus_fmt_is_420); + struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, const struct dw_hdmi_plat_data *plat_data) { diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c index 3d046878ce6c..b49bb0d86efe 100644 --- a/drivers/gpu/drm/meson/meson_dw_hdmi.c +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c @@ -379,8 +379,8 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, mode->clock > 340000 ? 40 : 10); if (drm_mode_is_420_only(display, mode) || - (!is_hdmi2_sink && - drm_mode_is_420_also(display, mode))) + (!is_hdmi2_sink && drm_mode_is_420_also(display, mode)) || + dw_hdmi_bus_fmt_is_420(hdmi)) mode_is_420 = true; /* Enable clocks */ diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h index f668e75fbabe..6a46baa0737c 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -206,4 +206,6 @@ void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, bool force, bool disabled, bool rxsense); void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data); +bool dw_hdmi_bus_fmt_is_420(struct dw_hdmi *hdmi); + #endif /* __IMX_HDMI_H__ */