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Signed-off-by: Jan Kiszka --- .../dts/ti/k3-am65-iot2050-common-pg2.dtsi | 18 ------------- .../boot/dts/ti/k3-am65-iot2050-usb3.dtsi | 27 +++++++++++++++++++ .../dts/ti/k3-am6528-iot2050-basic-pg2.dts | 1 + .../dts/ti/k3-am6548-iot2050-advanced-m2.dts | 13 --------- .../dts/ti/k3-am6548-iot2050-advanced-pg2.dts | 1 + 5 files changed, 29 insertions(+), 31 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am65-iot2050-usb3.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi index 42adb8815f38..93d966b67d8d 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi @@ -38,21 +38,3 @@ &dss { /* Workaround needed to get DP clock of 154Mhz */ assigned-clocks = <&k3_clks 67 0>; }; - -&serdes0 { - assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; - assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; -}; - -&dwc3_0 { - assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ - <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ - phys = <&serdes0 PHY_TYPE_USB3 0>; - phy-names = "usb3-phy"; -}; - -&usb0 { - maximum-speed = "super-speed"; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; -}; diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-usb3.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-usb3.dtsi new file mode 100644 index 000000000000..3f5fe4c38ebc --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-usb3.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Siemens AG, 2024 + * + * Authors: + * Jan Kiszka + * + * Common bits for IOT2050 variants with USB3 support + */ + +&serdes0 { + assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; +}; + +&dwc3_0 { + assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ + <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ + phys = <&serdes0 PHY_TYPE_USB3 0>; + phy-names = "usb3-phy"; +}; + +&usb0 { + maximum-speed = "super-speed"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-pg2.dts b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-pg2.dts index c62549a4b436..8be3370d3de1 100644 --- a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-pg2.dts +++ b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-pg2.dts @@ -17,6 +17,7 @@ #include "k3-am6528-iot2050-basic-common.dtsi" #include "k3-am65-iot2050-common-pg2.dtsi" +#include "k3-am65-iot2050-usb3.dtsi" / { compatible = "siemens,iot2050-basic-pg2", "ti,am654"; diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts index 2401cbe2b66c..38623501a14f 100644 --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts @@ -92,16 +92,3 @@ &pcie0_rc { &pcie1_rc { status = "disabled"; }; - -&dwc3_0 { - assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ - <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ - /delete-property/ phys; - /delete-property/ phy-names; -}; - -&usb0 { - maximum-speed = "high-speed"; - /delete-property/ snps,dis-u1-entry-quirk; - /delete-property/ snps,dis-u2-entry-quirk; -}; diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-pg2.dts b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-pg2.dts index c1205feef54e..b6e878a31c27 100644 --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-pg2.dts +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-pg2.dts @@ -18,6 +18,7 @@ #include "k3-am6548-iot2050-advanced-common.dtsi" #include "k3-am65-iot2050-common-pg2.dtsi" #include "k3-am65-iot2050-arduino-connector.dtsi" +#include "k3-am65-iot2050-usb3.dtsi" / { compatible = "siemens,iot2050-advanced-pg2", "ti,am654";