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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB4F.mail.protection.outlook.com (10.167.242.73) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7249.19 via Frontend Transport; Sun, 4 Feb 2024 12:13:15 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Sun, 4 Feb 2024 06:13:12 -0600 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v2 1/6] cpufreq: amd-pstate: initialize new core precision boost state Date: Sun, 4 Feb 2024 20:12:52 +0800 Message-ID: <51d8381943c3cfa7841775b02a414355f6baa20c.1707047943.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4F:EE_|DS0PR12MB7655:EE_ X-MS-Office365-Filtering-Correlation-Id: 3939e072-265f-41c0-4248-08dc257aaa92 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2024 12:13:15.7248 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3939e072-265f-41c0-4248-08dc257aaa92 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7655 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789970454944145371 X-GMAIL-MSGID: 1789970454944145371 From: Perry Yuan Add gloal global_params to represent current CPU Performance Boost(cpb) state for cpu frequency scaling, both active and passive modes all can support CPU cores frequency boosting control which is based on the BIOS setting, while BIOS turn on the "Core Performance Boost", it will allow OS control each core highest perf limitation from OS side. If core performance boost is disabled while a core is in a boosted P-state, the core transitions to the highest performance non-boosted P-state, that is the same as the nominal frequency limit. Reported-by: Artem S. Tashkinov" Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217931 Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 61 +++++++++++++++++------------------- 1 file changed, 28 insertions(+), 33 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 9a1e194d5cf8..921324ab9580 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -65,6 +65,19 @@ static struct cpufreq_driver amd_pstate_epp_driver; static int cppc_state = AMD_PSTATE_UNDEFINED; static bool cppc_enabled; +/** + * struct global_params - Global parameters, mostly tunable via sysfs. + * @cpb_boost: Whether or not to use boost CPU P-states. + * @cpb_supported: Whether or not CPU boost P-states are available + * based on the MSR_K7_HWCR bit[25] state + */ +struct global_params { + bool cpb_boost; + bool cpb_supported; +}; + +static struct global_params global; + /* * AMD Energy Preference Performance (EPP) * The EPP is used in the CCLK DPM controller to drive @@ -632,43 +645,21 @@ static int amd_get_lowest_nonlinear_freq(struct amd_cpudata *cpudata) return lowest_nonlinear_freq * 1000; } -static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) +static int amd_pstate_boost_init(struct amd_cpudata *cpudata) { - struct amd_cpudata *cpudata = policy->driver_data; + u64 boost_val; int ret; - if (!cpudata->boost_supported) { - pr_err("Boost mode is not supported by this processor or SBIOS\n"); - return -EINVAL; - } - - if (state) - policy->cpuinfo.max_freq = cpudata->max_freq; - else - policy->cpuinfo.max_freq = cpudata->nominal_freq; - - policy->max = policy->cpuinfo.max_freq; - - ret = freq_qos_update_request(&cpudata->req[1], - policy->cpuinfo.max_freq); - if (ret < 0) + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_K7_HWCR, &boost_val); + if (ret) { + pr_err_once("failed to read initial CPU boost state!\n"); return ret; + } - return 0; -} - -static void amd_pstate_boost_init(struct amd_cpudata *cpudata) -{ - u32 highest_perf, nominal_perf; - - highest_perf = READ_ONCE(cpudata->highest_perf); - nominal_perf = READ_ONCE(cpudata->nominal_perf); - - if (highest_perf <= nominal_perf) - return; + global.cpb_supported = !((boost_val >> 25) & 0x1); + global.cpb_boost = global.cpb_supported; - cpudata->boost_supported = true; - current_pstate_driver->boost_enabled = true; + return ret; } static void amd_perf_ctl_reset(unsigned int cpu) @@ -701,6 +692,9 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) if (ret) goto free_cpudata1; + /* initialize cpu cores boot state */ + amd_pstate_boost_init(cpudata); + min_freq = amd_get_min_freq(cpudata); max_freq = amd_get_max_freq(cpudata); nominal_freq = amd_get_nominal_freq(cpudata); @@ -750,7 +744,6 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) policy->driver_data = cpudata; - amd_pstate_boost_init(cpudata); if (!current_pstate_driver->adjust_perf) current_pstate_driver->adjust_perf = amd_pstate_adjust_perf; @@ -1118,6 +1111,9 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) if (ret) goto free_cpudata1; + /* initialize cpu cores boot state */ + amd_pstate_boost_init(cpudata); + min_freq = amd_get_min_freq(cpudata); max_freq = amd_get_max_freq(cpudata); nominal_freq = amd_get_nominal_freq(cpudata); @@ -1168,7 +1164,6 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) return ret; WRITE_ONCE(cpudata->cppc_cap1_cached, value); } - amd_pstate_boost_init(cpudata); return 0;