Message ID | 4c6674bf7e048e7370248e50ed3d011d604d020e.1683034376.git.michal.simek@amd.com |
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State | New |
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Tue, 2 May 2023 08:36:39 -0500 From: Michal Simek <michal.simek@amd.com> To: <linux-kernel@vger.kernel.org>, <monstr@monstr.eu>, <michal.simek@xilinx.com>, <git@xilinx.com> CC: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>, Harini Katakam <harini.katakam@amd.com>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Laurent Pinchart <laurent.pinchart@ideasonboard.com>, Parth Gajjar <parth.gajjar@amd.com>, Piyush Mehta <piyush.mehta@xilinx.com>, Rob Herring <robh+dt@kernel.org>, Robert Hancock <robert.hancock@calian.com>, Tanmay Shah <tanmay.shah@amd.com>, Vishal Sagar <vishal.sagar@amd.com>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org> Subject: [PATCH 07/23] arm64: zynqmp: Add pmu interrupt-affinity Date: Tue, 2 May 2023 15:35:35 +0200 Message-ID: <4c6674bf7e048e7370248e50ed3d011d604d020e.1683034376.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <cover.1683034376.git.michal.simek@amd.com> References: <cover.1683034376.git.michal.simek@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E636:EE_|LV3PR12MB9186:EE_ X-MS-Office365-Filtering-Correlation-Id: 97c3760f-735f-4a98-c258-08db4b124331 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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arm64: zynqmp: Misc zynqmp changes
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Commit Message
Michal Simek
May 2, 2023, 1:35 p.m. UTC
From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Explicitly specify interrupt affinity to avoid HW perfevents need to guess. This avoids the following error upon linux boot: armv8-pmu pmu: hw perfevents: no interrupt-affinity property, guessing. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
Comments
Hi Michal, Thank you for the patch. On Tue, May 02, 2023 at 03:35:35PM +0200, Michal Simek wrote: > From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > Explicitly specify interrupt affinity to avoid HW perfevents > need to guess. This avoids the following error upon linux boot: > armv8-pmu pmu: hw perfevents: no interrupt-affinity property, > guessing. As mentioned for some of the previous patches, the commit message should explain why this change improves the DT system description. The fact that it gets rid of a warning message may be mentioned, but it shouldn't be the main focus. > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > Signed-off-by: Michal Simek <michal.simek@amd.com> > --- > > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > index 61c7045eb992..a117294dc890 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > @@ -161,6 +161,10 @@ pmu { > <0 144 4>, > <0 145 4>, > <0 146 4>; > + interrupt-affinity = <&cpu0>, > + <&cpu1>, > + <&cpu2>, > + <&cpu3>; > }; > > psci {
On 5/2/23 15:35, Michal Simek wrote: > From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > > Explicitly specify interrupt affinity to avoid HW perfevents > need to guess. This avoids the following error upon linux boot: > armv8-pmu pmu: hw perfevents: no interrupt-affinity property, > guessing. > > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> > Signed-off-by: Michal Simek <michal.simek@amd.com> > --- > > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > index 61c7045eb992..a117294dc890 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > @@ -161,6 +161,10 @@ pmu { > <0 144 4>, > <0 145 4>, > <0 146 4>; > + interrupt-affinity = <&cpu0>, > + <&cpu1>, > + <&cpu2>, > + <&cpu3>; > }; > > psci { Applied. M
On 5/16/23 13:05, Michal Simek wrote: > > > On 5/2/23 15:35, Michal Simek wrote: >> From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> >> >> Explicitly specify interrupt affinity to avoid HW perfevents >> need to guess. This avoids the following error upon linux boot: >> armv8-pmu pmu: hw perfevents: no interrupt-affinity property, >> guessing. >> >> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> >> Signed-off-by: Michal Simek <michal.simek@amd.com> >> --- >> >> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >> b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >> index 61c7045eb992..a117294dc890 100644 >> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi >> @@ -161,6 +161,10 @@ pmu { >> <0 144 4>, >> <0 145 4>, >> <0 146 4>; >> + interrupt-affinity = <&cpu0>, >> + <&cpu1>, >> + <&cpu2>, >> + <&cpu3>; >> }; >> psci { > > Applied. > M Actually remove this one from my queue because there were comment from Laurent. M
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 61c7045eb992..a117294dc890 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -161,6 +161,10 @@ pmu { <0 144 4>, <0 145 4>, <0 146 4>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; }; psci {