From patchwork Wed Nov 23 04:10:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Asutosh Das X-Patchwork-Id: 24698 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp2583987wrr; Tue, 22 Nov 2022 20:17:31 -0800 (PST) X-Google-Smtp-Source: AA0mqf4cDk7jH4Ny1deWgBwJAzvNQhUUI0zql0vhQjW1ppE9zSyxNQE3oNfqU3GJ7FzScuK4/udO X-Received: by 2002:a17:906:860b:b0:7ad:f8e2:ff0a with SMTP id o11-20020a170906860b00b007adf8e2ff0amr22314366ejx.275.1669177050973; Tue, 22 Nov 2022 20:17:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669177050; cv=none; d=google.com; s=arc-20160816; b=MPWoPrrctt4iiLBqOY91tpS92kFtzYWPkI4LkuGLIMKBtmaTwrK4qTKjoosnnpc8PY aDApFX2R8Ct1h5dJgI28Ig3T3a161n+ps6pW4TzlWKO8yV5c0oBR5LFhKFjLFetX1V1s BSSSiGcRNg9OPJLSFtGVOh60kfkeSejXD2s0+q4XgNacZkzMuJ3VkMoP6FiAEf+RCTB4 mv5CS2vLMJ9mt6sSyfv8Z59+m3s73HAsuXLgcuC9TXv9kznQ/gZQQBrLxgVLEyk/pGLM mi4Y67+jukJISc5a3jC6HyIdpgUqfoCpkrxQ3wmOB1iQG0AbrLuhblX9B2srvPTJrNWH zlQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=t6xUOOZRttKGarxa9YabRslsDy5IMrqCimcg1B7TR8I=; b=toWHjwTU7jkZND2cfYHV6vJQrgdgz/Ww0uoH7zhLXPws6UrAB9LWNBo6KsSePWFWEy 4iyhJ0xdybgqCe/y4VWPW8eURSwT8I5laMZi8xF4MbFYrJqc0DR+FjteQiE8D9/h75uf t8jv9aqordw/7J1lnM1t5FoHrGr8Gfmi038k0ce3WzM047XmkGzIYg4dp+3d9/pPc7ZB V3wjYZFJdUjaFrnnQ82ERzqy+sn7DrcLA/MpwPJzhkOROjQmdINrLTF+T0GviTb6N46e j15e73UywEgF9nTIVQA/ecP19YR4Va+u/KeTLSiUh97oFMFXktbuoMMMGIvboAl7PysM rjmg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=IHYymd89; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id x1-20020a05640226c100b00458bb34ee93si14392063edd.149.2022.11.22.20.17.03; Tue, 22 Nov 2022 20:17:30 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=IHYymd89; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235877AbiKWEQP (ORCPT + 99 others); Tue, 22 Nov 2022 23:16:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235762AbiKWEPA (ORCPT ); Tue, 22 Nov 2022 23:15:00 -0500 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 04113EC7BB; Tue, 22 Nov 2022 20:13:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1669176827; x=1700712827; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=t6xUOOZRttKGarxa9YabRslsDy5IMrqCimcg1B7TR8I=; b=IHYymd899ivJP0tie1xs/omcUb1zicB6yFb9r87EaLEb85xqFWYj3ILu dhljQuoIhBpwr/7QjFZcBDPK0FnE4+sABSs6keN8SZasNongnu9BqeALQ 2dKCuVlfKG+0EefttYyJNt2h3P/0rPrLYvD0olEBODx+Q88aY8p/KGFoa U=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 22 Nov 2022 20:13:46 -0800 X-QCInternal: smtphost Received: from unknown (HELO nasanex01a.na.qualcomm.com) ([10.52.223.231]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Nov 2022 20:13:46 -0800 Received: from asutoshd-linux1.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 22 Nov 2022 20:13:46 -0800 From: Asutosh Das To: , , CC: , , , , , , , , , Asutosh Das , , Alim Akhtar , "James E.J. Bottomley" , Jinyoung Choi , Krzysztof Kozlowski , Arthur Simchaev , open list Subject: [PATCH v5 12/16] ufs: core: mcq: Find hardware queue to queue request Date: Tue, 22 Nov 2022 20:10:25 -0800 Message-ID: <479ce0c60d1be1c182f55efa9b53dd4850bb8f12.1669176158.git.quic_asutoshd@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750258995210202022?= X-GMAIL-MSGID: =?utf-8?q?1750258995210202022?= Adds support to find the hardware queue on which the request would be queued. Since the very first queue is to serve device commands, an offset of 1 is added to the index of the hardware queue. Co-developed-by: Can Guo Signed-off-by: Can Guo Signed-off-by: Asutosh Das Reviewed-by: Bart Van Assche Reviewed-by: Manivannan Sadhasivam --- drivers/ufs/core/ufs-mcq.c | 20 ++++++++++++++++++++ drivers/ufs/core/ufshcd-priv.h | 3 +++ drivers/ufs/core/ufshcd.c | 3 +++ 3 files changed, 26 insertions(+) diff --git a/drivers/ufs/core/ufs-mcq.c b/drivers/ufs/core/ufs-mcq.c index 7179f86..10a0d0d7 100644 --- a/drivers/ufs/core/ufs-mcq.c +++ b/drivers/ufs/core/ufs-mcq.c @@ -94,6 +94,26 @@ static const struct ufshcd_res_info ufs_res_info[RES_MAX] = { }; /** + * ufshcd_mcq_req_to_hwq - find the hardware queue on which the + * request would be issued. + * @hba - per adapter instance + * @req - pointer to the request to be issued + * + * Returns the hardware queue instance on which the request would + * be queued. + */ +struct ufs_hw_queue *ufshcd_mcq_req_to_hwq(struct ufs_hba *hba, + struct request *req) +{ + u32 utag = blk_mq_unique_tag(req); + u32 hwq = blk_mq_unique_tag_to_hwq(utag); + + /* uhq[0] is used to serve device commands */ + return &hba->uhq[hwq + UFSHCD_MCQ_IO_QUEUE_OFFSET]; +} + + +/** * ufshcd_mcq_decide_queue_depth - decide the queue depth * @hba - per adapter instance * diff --git a/drivers/ufs/core/ufshcd-priv.h b/drivers/ufs/core/ufshcd-priv.h index 5616047..14df7ce 100644 --- a/drivers/ufs/core/ufshcd-priv.h +++ b/drivers/ufs/core/ufshcd-priv.h @@ -67,7 +67,10 @@ int ufshcd_mcq_memory_alloc(struct ufs_hba *hba); void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba); void ufshcd_mcq_config_mac(struct ufs_hba *hba, u32 max_active_cmds); void ufshcd_mcq_select_mcq_mode(struct ufs_hba *hba); +struct ufs_hw_queue *ufshcd_mcq_req_to_hwq(struct ufs_hba *hba, + struct request *req); +#define UFSHCD_MCQ_IO_QUEUE_OFFSET 1 #define SD_ASCII_STD true #define SD_RAW false int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index 93a9e38..52c0386 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -2921,6 +2921,9 @@ static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) goto out; } + if (is_mcq_enabled(hba)) + hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd)); + ufshcd_send_command(hba, tag, hwq); out: