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Mon, 13 Nov 2023 05:19:09 -0800 (PST) From: Chen Wang <unicornxw@gmail.com> To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, palmer@dabbelt.com, paul.walmsley@sifive.com, richardcochran@gmail.com, robh+dt@kernel.org, sboyd@kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com Cc: Chen Wang <unicorn_wang@outlook.com> Subject: [PATCH 2/5] dt-bindings: soc: sophgo: Add Sophgo syscon module Date: Mon, 13 Nov 2023 21:19:02 +0800 Message-Id: <3c286171af30101b88f0aaf645fb0a7d5880ac0a.1699879741.git.unicorn_wang@outlook.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <cover.1699879741.git.unicorn_wang@outlook.com> References: <cover.1699879741.git.unicorn_wang@outlook.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-0.6 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); 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Series |
riscv: sophgo: add clock support for sg2042
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Commit Message
Chen Wang
Nov. 13, 2023, 1:19 p.m. UTC
From: Chen Wang <unicorn_wang@outlook.com> Add documentation to describe Sophgo System Controller Registers for SG2042. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> --- .../soc/sophgo/sophgo,sg2042-syscon.yaml | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml
Comments
On Mon, Nov 13, 2023 at 09:19:02PM +0800, Chen Wang wrote: > From: Chen Wang <unicorn_wang@outlook.com> > > Add documentation to describe Sophgo System Controller Registers for > SG2042. > > Signed-off-by: Chen Wang <unicorn_wang@outlook.com> > --- > .../soc/sophgo/sophgo,sg2042-syscon.yaml | 38 +++++++++++++++++++ > 1 file changed, 38 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml > > diff --git a/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml b/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml > new file mode 100644 > index 000000000000..829abede4fd5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml > @@ -0,0 +1,38 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/sophgo/sophgo,sg2042-syscon.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Sophgo SG2042 SoC system controller > + > +maintainers: > + - Chen Wang <unicorn_wang@outlook.com> > + > +description: > + The Sophgo SG2042 SoC system controller provides register information such > + as offset, mask and shift to configure related modules. > + > +properties: > + compatible: > + oneOf: > + - items: > + - enum: > + - sophgo,sg2042-syscon > + - const: syscon THere's only one option here, so the oneOf should be removed. Similarly, since there's only one SoC, and it sounds like the next large sophgo system is going to be using an entirely different core provider, I think should just simplify this to a pair of "const:" entries. > + > + reg: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + > +additionalProperties: false > + > +examples: > + - | > + syscon@30010000 { > + compatible = "sophgo,sg2042-syscon", "syscon"; > + reg = <0x30010000 0x1000>; > + }; Per my comments elsewhere, I think the clock controller should be a child of this node, rather than an unrelated node, linked by a phandle. Cheers, Conor.
On 2023/11/15 1:40, Conor Dooley wrote: > On Mon, Nov 13, 2023 at 09:19:02PM +0800, Chen Wang wrote: >> From: Chen Wang <unicorn_wang@outlook.com> >> >> Add documentation to describe Sophgo System Controller Registers for >> SG2042. >> >> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> >> --- >> .../soc/sophgo/sophgo,sg2042-syscon.yaml | 38 +++++++++++++++++++ >> 1 file changed, 38 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml >> >> diff --git a/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml b/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml >> new file mode 100644 >> index 000000000000..829abede4fd5 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml >> @@ -0,0 +1,38 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/soc/sophgo/sophgo,sg2042-syscon.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Sophgo SG2042 SoC system controller >> + >> +maintainers: >> + - Chen Wang <unicorn_wang@outlook.com> >> + >> +description: >> + The Sophgo SG2042 SoC system controller provides register information such >> + as offset, mask and shift to configure related modules. >> + >> +properties: >> + compatible: >> + oneOf: >> + - items: >> + - enum: >> + - sophgo,sg2042-syscon >> + - const: syscon > THere's only one option here, so the oneOf should be removed. Similarly, > since there's only one SoC, and it sounds like the next large sophgo > system is going to be using an entirely different core provider, I think > should just simplify this to a pair of "const:" entries. Yes, "oneOf" should be removed. Regarding the "enum", I heard from Sophgo people, that they will announce a new SG2044 chip next year and it will share some modules from SG2042, including syscon, clock ... So it is better keeping the "enum" here and we may add another "sophgo,sg2044-syscon" later. Regarding the next large sophgo system you mentioned, yes, there is anther chip, I think you are talking about SG2380, it will use core(P670) from SiFive. Maybe we can see it in next year also. More news, I find a report from web: https://www.hpcwire.com/2023/11/13/chinese-company-developing-64-core-risc-v-chip-with-tech-from-u-s/, FYI. >> + >> + reg: >> + maxItems: 1 >> + >> +required: >> + - compatible >> + - reg >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + syscon@30010000 { >> + compatible = "sophgo,sg2042-syscon", "syscon"; >> + reg = <0x30010000 0x1000>; >> + }; > Per my comments elsewhere, I think the clock controller should be a > child of this node, rather than an unrelated node, linked by a phandle. Agree, I will correct this in next revision. > > Cheers, > Conor.
On Tue, Nov 14, 2023 at 05:40:20PM +0000, Conor Dooley wrote: > On Mon, Nov 13, 2023 at 09:19:02PM +0800, Chen Wang wrote: > > From: Chen Wang <unicorn_wang@outlook.com> > > > > Add documentation to describe Sophgo System Controller Registers for > > SG2042. > > > > Signed-off-by: Chen Wang <unicorn_wang@outlook.com> > > --- > > .../soc/sophgo/sophgo,sg2042-syscon.yaml | 38 +++++++++++++++++++ > > 1 file changed, 38 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml > > > > diff --git a/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml b/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml > > new file mode 100644 > > index 000000000000..829abede4fd5 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml > > @@ -0,0 +1,38 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/soc/sophgo/sophgo,sg2042-syscon.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Sophgo SG2042 SoC system controller > > + > > +maintainers: > > + - Chen Wang <unicorn_wang@outlook.com> > > + > > +description: > > + The Sophgo SG2042 SoC system controller provides register information such > > + as offset, mask and shift to configure related modules. > > + > > +properties: > > + compatible: > > + oneOf: > > + - items: > > + - enum: > > + - sophgo,sg2042-syscon > > + - const: syscon > > THere's only one option here, so the oneOf should be removed. Similarly, > since there's only one SoC, and it sounds like the next large sophgo > system is going to be using an entirely different core provider, I think > should just simplify this to a pair of "const:" entries. For a simple syscon binding like this, you can just add the compatible to syscon.yaml. Rob
diff --git a/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml b/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml new file mode 100644 index 000000000000..829abede4fd5 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2042-syscon.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/sophgo/sophgo,sg2042-syscon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 SoC system controller + +maintainers: + - Chen Wang <unicorn_wang@outlook.com> + +description: + The Sophgo SG2042 SoC system controller provides register information such + as offset, mask and shift to configure related modules. + +properties: + compatible: + oneOf: + - items: + - enum: + - sophgo,sg2042-syscon + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@30010000 { + compatible = "sophgo,sg2042-syscon", "syscon"; + reg = <0x30010000 0x1000>; + };