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[2620:137:e000::1:20]) by mx.google.com with ESMTP id i11-20020a50870b000000b00451e1aae675si3484460edb.547.2022.10.29.23.30.00; Sat, 29 Oct 2022 23:30:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=COwfKpvq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230241AbiJ3G32 (ORCPT + 99 others); Sun, 30 Oct 2022 02:29:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47722 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230336AbiJ3G0Q (ORCPT ); Sun, 30 Oct 2022 02:26:16 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB383283; Sat, 29 Oct 2022 23:24:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667111059; x=1698647059; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0uHShJOfWkZALFatNyLGZvdWrcXhZtI8MbG7lnSItHY=; b=COwfKpvqTCWZ+NF+RQcj00EKTzlrJ6d76A6AAcSGNPhUlXauvhclrUEI kvEnyTCppBRKGoCTkGkt9JFn9+eOnURjkVdtgCpbp/kXIXBHTYkwt+R0/ TroGb+PYXD/rErQo83O6s2pSh5C2z8cZwIV3K/ngroPyuuVobWC0Wa3KS rpfCA0QbLCt5SG4vKcfHz/C64eqUb3Ea3FTgHOiG/6bqQS6gjynHgMcFF bH/uXfS55jCa2GAk0IVQ6UVM9w/XUA1JUnWDP5YoRfud2A6RjvCrgiXFQ 3CZDCPe2eQNh4MYeVSLcfY7AHCK8FpmeUAMOf1OLy5+rYUNmug/Fz9SfX w==; X-IronPort-AV: E=McAfee;i="6500,9779,10515"; a="395037178" X-IronPort-AV: E=Sophos;i="5.95,225,1661842800"; d="scan'208";a="395037178" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Oct 2022 23:24:08 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10515"; a="878393054" X-IronPort-AV: E=Sophos;i="5.95,225,1661842800"; d="scan'208";a="878393054" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Oct 2022 23:24:08 -0700 From: isaku.yamahata@intel.com To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, Paolo Bonzini , erdemaktas@google.com, Sean Christopherson , Sagi Shahar , David Matlack Subject: [PATCH v10 065/108] KVM: TDX: Finalize VM initialization Date: Sat, 29 Oct 2022 23:23:06 -0700 Message-Id: <3b1e9bc1488e592faac5ec2df5c94f88f3276ea4.1667110240.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748093028759377395?= X-GMAIL-MSGID: =?utf-8?q?1748093028759377395?= From: Isaku Yamahata To protect the initial contents of the guest TD, the TDX module measures the guest TD during the build process as SHA-384 measurement. The measurement of the guest TD contents needs to be completed to make the guest TD ready to run. Add a new subcommand, KVM_TDX_FINALIZE_VM, for VM-scoped KVM_MEMORY_ENCRYPT_OP to finalize the measurement and mark the TDX VM ready to run. Signed-off-by: Isaku Yamahata --- arch/x86/include/uapi/asm/kvm.h | 1 + arch/x86/kvm/vmx/tdx.c | 31 +++++++++++++++++++++++++++ tools/arch/x86/include/uapi/asm/kvm.h | 1 + 3 files changed, 33 insertions(+) diff --git a/arch/x86/include/uapi/asm/kvm.h b/arch/x86/include/uapi/asm/kvm.h index 6ae52926e05a..a8e3945a3ea2 100644 --- a/arch/x86/include/uapi/asm/kvm.h +++ b/arch/x86/include/uapi/asm/kvm.h @@ -541,6 +541,7 @@ enum kvm_tdx_cmd_id { KVM_TDX_INIT_VM, KVM_TDX_INIT_VCPU, KVM_TDX_INIT_MEM_REGION, + KVM_TDX_FINALIZE_VM, KVM_TDX_CMD_NR_MAX, }; diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c index 7c00f71d42af..cce6ccd4a0be 100644 --- a/arch/x86/kvm/vmx/tdx.c +++ b/arch/x86/kvm/vmx/tdx.c @@ -1236,6 +1236,34 @@ static int tdx_init_mem_region(struct kvm *kvm, struct kvm_tdx_cmd *cmd) return ret; } +static int tdx_td_finalizemr(struct kvm *kvm) +{ + struct kvm_tdx *kvm_tdx = to_kvm_tdx(kvm); + u64 err; + + if (!is_td_initialized(kvm) || is_td_finalized(kvm_tdx)) + return -EINVAL; + + err = tdh_mr_finalize(kvm_tdx->tdr.pa); + if (WARN_ON_ONCE(err)) { + pr_tdx_error(TDH_MR_FINALIZE, err, NULL); + return -EIO; + } + + /* + * Blindly do TDH_MEM_TRACK after finalizing the measurement to handle + * the case where SEPT entries were zapped/blocked, e.g. from failed + * NUMA balancing, after they were added to the TD via + * tdx_init_mem_region(). TDX module doesn't allow TDH_MEM_TRACK prior + * to TDH.MR.FINALIZE, and conversely requires TDH.MEM.TRACK for entries + * that were TDH.MEM.RANGE.BLOCK'd prior to TDH.MR.FINALIZE. + */ + (void)tdh_mem_track(to_kvm_tdx(kvm)->tdr.pa); + + kvm_tdx->finalized = true; + return 0; +} + int tdx_vm_ioctl(struct kvm *kvm, void __user *argp) { struct kvm_tdx_cmd tdx_cmd; @@ -1255,6 +1283,9 @@ int tdx_vm_ioctl(struct kvm *kvm, void __user *argp) case KVM_TDX_INIT_MEM_REGION: r = tdx_init_mem_region(kvm, &tdx_cmd); break; + case KVM_TDX_FINALIZE_VM: + r = tdx_td_finalizemr(kvm); + break; default: r = -EINVAL; goto out; diff --git a/tools/arch/x86/include/uapi/asm/kvm.h b/tools/arch/x86/include/uapi/asm/kvm.h index 37e713ffab72..0aeb4639be89 100644 --- a/tools/arch/x86/include/uapi/asm/kvm.h +++ b/tools/arch/x86/include/uapi/asm/kvm.h @@ -541,6 +541,7 @@ enum kvm_tdx_cmd_id { KVM_TDX_INIT_VM, KVM_TDX_INIT_VCPU, KVM_TDX_INIT_MEM_REGION, + KVM_TDX_FINALIZE_VM, KVM_TDX_CMD_NR_MAX, };