[rdma-next,08/13] RDMA/mlx5: Add cryptographic device capabilities
Commit Message
From: Israel Rukshin <israelr@nvidia.com>
The capabilities provide information on general cryptographic support,
maximum number of DEKs and status for RDMA devices. Also, they include
the supported cryptographic engines and their import method (wrapped or
plaintext). Wrapped crypto operational flag indicates the import method
mode that can be used. For now, add only AES-XTS cryptographic support.
Signed-off-by: Israel Rukshin <israelr@nvidia.com>
Signed-off-by: Leon Romanovsky <leon@kernel.org>
---
drivers/infiniband/hw/mlx5/Makefile | 1 +
drivers/infiniband/hw/mlx5/crypto.c | 31 ++++++++++++++++++++++++++++
drivers/infiniband/hw/mlx5/crypto.h | 11 ++++++++++
drivers/infiniband/hw/mlx5/main.c | 5 +++++
drivers/infiniband/hw/mlx5/mlx5_ib.h | 2 ++
5 files changed, 50 insertions(+)
create mode 100644 drivers/infiniband/hw/mlx5/crypto.c
create mode 100644 drivers/infiniband/hw/mlx5/crypto.h
@@ -6,6 +6,7 @@ mlx5_ib-y := ah.o \
cong.o \
counters.o \
cq.o \
+ crypto.o \
dm.o \
doorbell.o \
gsi.o \
new file mode 100644
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
+/* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. */
+
+#include "crypto.h"
+
+void mlx5r_crypto_caps_init(struct mlx5_ib_dev *dev)
+{
+ struct ib_crypto_caps *caps = &dev->crypto_caps;
+ struct mlx5_core_dev *mdev = dev->mdev;
+
+ if (!(MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
+ MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY))
+ return;
+
+ if (!MLX5_CAP_GEN(mdev, aes_xts_multi_block_le_tweak) &&
+ !MLX5_CAP_GEN(mdev, aes_xts_multi_block_be_tweak))
+ return;
+
+ if (MLX5_CAP_CRYPTO(mdev, wrapped_import_method) &
+ MLX5_CRYPTO_WRAPPED_IMPORT_METHOD_CAP_AES_XTS)
+ return;
+
+ if (MLX5_CAP_CRYPTO(mdev, failed_selftests)) {
+ mlx5_ib_warn(dev, "crypto self-tests failed with error 0x%x\n",
+ MLX5_CAP_CRYPTO(mdev, failed_selftests));
+ return;
+ }
+
+ caps->crypto_engines |= IB_CRYPTO_ENGINES_CAP_AES_XTS;
+ caps->max_num_deks = 1 << MLX5_CAP_CRYPTO(mdev, log_max_num_deks);
+}
new file mode 100644
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
+/* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. */
+
+#ifndef _MLX5_IB_CRYPTO_H
+#define _MLX5_IB_CRYPTO_H
+
+#include "mlx5_ib.h"
+
+void mlx5r_crypto_caps_init(struct mlx5_ib_dev *dev);
+
+#endif /* _MLX5_IB_CRYPTO_H */
@@ -39,6 +39,7 @@
#include "srq.h"
#include "qp.h"
#include "wr.h"
+#include "crypto.h"
#include "restrack.h"
#include "counters.h"
#include "umr.h"
@@ -989,6 +990,7 @@ static int mlx5_ib_query_device(struct ib_device *ibdev,
props->max_ah = INT_MAX;
props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
+ props->crypto_caps = dev->crypto_caps;
if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
if (dev->odp_caps.general_caps & IB_ODP_SUPPORT)
@@ -3826,6 +3828,9 @@ static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
if (MLX5_CAP_GEN(mdev, xrc))
ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
+ if (MLX5_CAP_GEN(mdev, crypto))
+ mlx5r_crypto_caps_init(dev);
+
if (MLX5_CAP_DEV_MEM(mdev, memic) ||
MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
@@ -1100,6 +1100,8 @@ struct mlx5_ib_dev {
struct mlx5_ib_delay_drop delay_drop;
const struct mlx5_ib_profile *profile;
+ struct ib_crypto_caps crypto_caps;
+
struct mlx5_ib_lb_state lb;
u8 umr_fence;
struct list_head ib_dev_list;