[v7,4/4] riscv: dts: add clock generator for Sophgo SG2042 SoC
Commit Message
From: Chen Wang <unicorn_wang@outlook.com>
Add clock generator node to device tree for SG2042, and enable clock for
uart.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---
.../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 4 ++++
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 23 +++++++++++++++++++
2 files changed, 27 insertions(+)
Comments
On Mon, Jan 08, 2024 at 02:49:53PM +0800, Chen Wang wrote:
> + cgi: oscillator {
> + compatible = "fixed-clock";
> + clock-output-names = "cgi";
> + #clock-cells = <0>;
> + };
Where does the name "cgi" come from and what does it mean?
Clock Generator Input? Does the sg2042 documentation call it that?
Cheers,
Conor.
On 2024/1/10 22:13, Conor Dooley wrote:
> On Mon, Jan 08, 2024 at 02:49:53PM +0800, Chen Wang wrote:
>
>> + cgi: oscillator {
>> + compatible = "fixed-clock";
>> + clock-output-names = "cgi";
>> + #clock-cells = <0>;
>> + };
> Where does the name "cgi" come from and what does it mean?
> Clock Generator Input? Does the sg2042 documentation call it that?
It's abbrevation of "Clock Gen IC", I found this in the clock tree
diagram.
https://github.com/sophgo/sophgo-doc/blob/main/SG2042/TRM/source/pic/clock-tree.png
BTW, There are three cgi on the diagram. Should I define 3 in DTS too? I
just found they are the same so I just defined one.
>
> Cheers,
> Conor.
@@ -14,6 +14,10 @@ chosen {
};
};
+&cgi {
+ clock-frequency = <25000000>;
+};
+
&uart0 {
status = "okay";
};
@@ -5,6 +5,7 @@
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
#include "sg2042-cpus.dtsi"
@@ -18,6 +19,12 @@ aliases {
serial0 = &uart0;
};
+ cgi: oscillator {
+ compatible = "fixed-clock";
+ clock-output-names = "cgi";
+ #clock-cells = <0>;
+ };
+
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -311,12 +318,28 @@ intc: interrupt-controller@7090000000 {
riscv,ndev = <224>;
};
+ sys_ctrl: system-controller@7030010000 {
+ compatible = "sophgo,sg2042-sysctrl";
+ reg = <0x70 0x30010000 0x0 0x1000>;
+ };
+
+ clkgen: clock-controller@7030012000 {
+ compatible = "sophgo,sg2042-clkgen";
+ reg = <0x70 0x30012000 0x0 0x1000>;
+ sophgo,system-ctrl = <&sys_ctrl>;
+ #clock-cells = <1>;
+ clocks = <&cgi>;
+ };
+
uart0: serial@7040000000 {
compatible = "snps,dw-apb-uart";
reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
interrupt-parent = <&intc>;
interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
+ clocks = <&clkgen GATE_CLK_UART_500M>,
+ <&clkgen GATE_CLK_APB_UART>;
+ clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";