diff mbox series

x86/msr-index: Fix the order of ARCH_CAP_XAPIC_DISABLE bit

Message ID 243317ff6c8db307b7701a45f71e5c21da80194b.1705632532.git.pawan.kumar.gupta@linux.intel.com
State New
Headers
Series x86/msr-index: Fix the order of ARCH_CAP_XAPIC_DISABLE bit |

Commit Message

Pawan Gupta Jan. 19, 2024, 2:52 a.m. UTC 
  XAPIC_DISABLE bit of MSR_IA32_ARCH_CAP is not in correct order, fix it.

No functional change.

Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
---
 arch/x86/include/asm/msr-index.h | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)


base-commit: 0dd3ee31125508cd67f7e7172247f05b7fd1753a
diff mbox series

Patch

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 1d51e1850ed0..c72d68fc774f 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -152,6 +152,10 @@ 
 						 * are restricted to targets in
 						 * kernel.
 						 */
+#define ARCH_CAP_XAPIC_DISABLE		BIT(21)	/*
+						 * IA32_XAPIC_DISABLE_STATUS MSR
+						 * supported
+						 */
 #define ARCH_CAP_PBRSB_NO		BIT(24)	/*
 						 * Not susceptible to Post-Barrier
 						 * Return Stack Buffer Predictions.
@@ -166,11 +170,6 @@ 
 						 * Data Sampling (GDS).
 						 */
 
-#define ARCH_CAP_XAPIC_DISABLE		BIT(21)	/*
-						 * IA32_XAPIC_DISABLE_STATUS MSR
-						 * supported
-						 */
-
 #define MSR_IA32_FLUSH_CMD		0x0000010b
 #define L1D_FLUSH			BIT(0)	/*
 						 * Writeback and invalidate the