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AJvYcCWKkroTKCxqAla1vvsVuSxJFASKHpPNF7VatvoK7hzyrZkJBCslxdNId3FuGt6whkHDO4B059UPQVX98WIYnG/4UhtZOq8V/JiPdof2 X-Gm-Message-State: AOJu0Yx7fZ7Ov1/HDwHvVsXR51Q7tTXuCay15pjz2vRl2iKKHlMqY7IK EfBhLXoq5dn5n/U/MwQTLMmzL7R7yBT5bz77pcxb4nSspg6Q0lsqUzQYRwEGInQs3Gr3nGIx0MU jegvyLA== X-Received: from irogers.svl.corp.google.com ([2620:15c:2a3:200:af4b:7fc1:b7be:fcb7]) (user=irogers job=sendgmr) by 2002:a81:7908:0:b0:609:2cab:1bd7 with SMTP id u8-20020a817908000000b006092cab1bd7mr635579ywc.1.1709319418022; Fri, 01 Mar 2024 10:56:58 -0800 (PST) Date: Fri, 1 Mar 2024 10:55:57 -0800 In-Reply-To: <20240301185559.2661241-1-irogers@google.com> Message-Id: <20240301185559.2661241-19-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240301185559.2661241-1-irogers@google.com> X-Mailer: git-send-email 2.44.0.278.ge034bb2e1d-goog Subject: [PATCH v2 18/20] perf jevents: Add C-State metrics from the PCU PMU for Intel From: Ian Rogers To: Perry Taylor , Samantha Alt , Caleb Biggers , Weilin Wang , Edward Baker , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , John Garry , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Stephane Eranian X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792351608848860389 X-GMAIL-MSGID: 1792351608848860389 Use occupancy events fixed in: https://lore.kernel.org/lkml/20240226201517.3540187-1-irogers@google.com/ Metrics are at the socket level referring to cores, not hyperthreads. Signed-off-by: Ian Rogers --- tools/perf/pmu-events/intel_metrics.py | 27 ++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/tools/perf/pmu-events/intel_metrics.py b/tools/perf/pmu-events/intel_metrics.py index 8086aef3557a..2e076f695292 100755 --- a/tools/perf/pmu-events/intel_metrics.py +++ b/tools/perf/pmu-events/intel_metrics.py @@ -784,6 +784,32 @@ def IntelLdSt() -> Optional[MetricGroup]: ], description = "Breakdown of load/store instructions") +def UncoreCState() -> Optional[MetricGroup]: + try: + pcu_ticks = Event("UNC_P_CLOCKTICKS") + c0 = Event("UNC_P_POWER_STATE_OCCUPANCY.CORES_C0") + c3 = Event("UNC_P_POWER_STATE_OCCUPANCY.CORES_C3") + c6 = Event("UNC_P_POWER_STATE_OCCUPANCY.CORES_C6") + except: + return None + + num_cores = Literal("#num_cores") / Literal("#num_packages") + + max_cycles = pcu_ticks * num_cores; + total_cycles = c0 + c3 + c6 + + # remove fused-off cores which show up in C6/C7. + c6 = Select(max(c6 - (total_cycles - max_cycles), 0), + total_cycles > max_cycles, + c6) + + return MetricGroup("cstate", [ + Metric("cstate_c0", "C-State cores in C0/C1", d_ratio(c0, pcu_ticks), "cores"), + Metric("cstate_c3", "C-State cores in C3", d_ratio(c3, pcu_ticks), "cores"), + Metric("cstate_c6", "C-State cores in C6/C7", d_ratio(c6, pcu_ticks), "cores"), + ]) + + def UncoreDir() -> Optional[MetricGroup]: try: m2m_upd = Event("UNC_M2M_DIRECTORY_UPDATE.ANY") @@ -920,6 +946,7 @@ all_metrics = MetricGroup("", [ IntelMlp(), IntelPorts(), IntelSwpf(), + UncoreCState(), UncoreDir(), UncoreMem(), UncoreMemBw(),