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[v5,11/13] riscv: mm: Make asid_bits a local variable

Message ID	20240229232211.161961-12-samuel.holland@sifive.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel+bounces-87682-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) client-ip=2604:1380:40f1:3f00::1; From: Samuel Holland <samuel.holland@sifive.com> To: Palmer Dabbelt <palmer@dabbelt.com>, linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, linux-mm@kvack.org, Alexandre Ghiti <alexghiti@rivosinc.com>, Jisheng Zhang <jszhang@kernel.org>, Yunhui Cui <cuiyunhui@bytedance.com>, Samuel Holland <samuel.holland@sifive.com> Subject: [PATCH v5 11/13] riscv: mm: Make asid_bits a local variable Date: Thu, 29 Feb 2024 15:21:52 -0800 Message-ID: <20240229232211.161961-12-samuel.holland@sifive.com> In-Reply-To: <20240229232211.161961-1-samuel.holland@sifive.com> References: <20240229232211.161961-1-samuel.holland@sifive.com> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-getmail-retrieved-from-mailbox: INBOX
Series	riscv: ASID-related and UP-related TLB flush enhancements \| [v5,00/13] riscv: ASID-related and UP-related TLB flush enhancements [v5,01/13] riscv: Flush the instruction cache during SMP bringup [v5,02/13] riscv: Factor out page table TLB synchronization [v5,03/13] riscv: Use IPIs for remote cache/TLB flushes by default [v5,04/13] riscv: mm: Broadcast kernel TLB flushes only when needed [v5,05/13] riscv: Only send remote fences when some other CPU is online [v5,06/13] riscv: mm: Combine the SMP and UP TLB flush code [v5,07/13] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma [v5,08/13] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 [v5,09/13] riscv: mm: Introduce cntx2asid/cntx2version helper macros [v5,10/13] riscv: mm: Use a fixed layout for the MM context ID [v5,11/13] riscv: mm: Make asid_bits a local variable [v5,12/13] riscv: mm: Preserve global TLB entries when switching contexts [v5,13/13] riscv: mm: Always use an ASID to flush mm contexts

Commit Message

Samuel Holland Feb. 29, 2024, 11:21 p.m. UTC

  This variable is only used inside asids_init().

Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---

(no changes since v1)

 arch/riscv/mm/context.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

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Patch

diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c
index 5315af06cd4d..0bf6d0070a14 100644
--- a/arch/riscv/mm/context.c
+++ b/arch/riscv/mm/context.c
@@ -20,7 +20,6 @@ 
 
 DEFINE_STATIC_KEY_FALSE(use_asid_allocator);
 
-static unsigned long asid_bits;
 static unsigned long num_asids;
 
 static atomic_long_t current_version;
@@ -226,7 +225,7 @@  static inline void set_mm(struct mm_struct *prev,
 
 static int __init asids_init(void)
 {
-	unsigned long old;
+	unsigned long asid_bits, old;
 
 	/* Figure-out number of ASID bits in HW */
 	old = csr_read(CSR_SATP);