diff mbox series

[v4,02/15] RISC-V: Add FIRMWARE_READ_HI definition

Message ID	20240229010130.1380926-3-atishp@rivosinc.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel+bounces-85969-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) client-ip=2604:1380:45e3:2400::1; From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, Conor Dooley <conor.dooley@microchip.com>, Anup Patel <anup@brainfault.org>, Albert Ou <aou@eecs.berkeley.edu>, Alexandre Ghiti <alexghiti@rivosinc.com>, Andrew Jones <ajones@ventanamicro.com>, Atish Patra <atishp@atishpatra.org>, Guo Ren <guoren@kernel.org>, Icenowy Zheng <uwu@icenowy.me>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paolo Bonzini <pbonzini@redhat.com>, Paul Walmsley <paul.walmsley@sifive.com>, Shuah Khan <shuah@kernel.org>, Will Deacon <will@kernel.org> Subject: [PATCH v4 02/15] RISC-V: Add FIRMWARE_READ_HI definition Date: Wed, 28 Feb 2024 17:01:17 -0800 Message-Id: <20240229010130.1380926-3-atishp@rivosinc.com> In-Reply-To: <20240229010130.1380926-1-atishp@rivosinc.com> References: <20240229010130.1380926-1-atishp@rivosinc.com> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-getmail-retrieved-from-mailbox: INBOX
Series	RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest \| [v4,00/15] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest [v4,01/15] RISC-V: Fix the typo in Scountovf CSR name [v4,02/15] RISC-V: Add FIRMWARE_READ_HI definition [v4,03/15] drivers/perf: riscv: Read upper bits of a firmware counter [v4,05/15] drivers/perf: riscv: Implement SBI PMU snapshot function [v4,07/15] RISC-V: KVM: No need to exit to the user space if perf event failed [v4,08/15] RISC-V: KVM: Implement SBI PMU Snapshot feature [v4,09/15] RISC-V: KVM: Add perf sampling support for guests [v4,10/15] RISC-V: KVM: Support 64 bit firmware counters on RV32 [v4,11/15] KVM: riscv: selftests: Add Sscofpmf to get-reg-list test [v4,12/15] KVM: riscv: selftests: Add SBI PMU extension definitions [v4,13/15] KVM: riscv: selftests: Add SBI PMU selftest [v4,15/15] KVM: riscv: selftests: Add a test for counter overflow

Commit Message

Atish Patra Feb. 29, 2024, 1:01 a.m. UTC

  SBI v2.0 added another function to SBI PMU extension to read
the upper bits of a counter with width larger than XLEN.

Add the definition for that function.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 arch/riscv/include/asm/sbi.h | 1 +
 1 file changed, 1 insertion(+)

Comments

Clément Léger March 1, 2024, 8:27 a.m. UTC | #1

On 29/02/2024 02:01, Atish Patra wrote:
> SBI v2.0 added another function to SBI PMU extension to read
> the upper bits of a counter with width larger than XLEN.
> 
> Add the definition for that function.
> 
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
>  arch/riscv/include/asm/sbi.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index 6e68f8dff76b..ef8311dafb91 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -131,6 +131,7 @@ enum sbi_ext_pmu_fid {
>  	SBI_EXT_PMU_COUNTER_START,
>  	SBI_EXT_PMU_COUNTER_STOP,
>  	SBI_EXT_PMU_COUNTER_FW_READ,
> +	SBI_EXT_PMU_COUNTER_FW_READ_HI,
>  };
>  
>  union sbi_pmu_ctr_info {

Reviewed-by: Clément Léger <cleger@rivosinc.com>

Thanks,

Clément

diff mbox series

Patch

diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 6e68f8dff76b..ef8311dafb91 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -131,6 +131,7 @@  enum sbi_ext_pmu_fid {
 	SBI_EXT_PMU_COUNTER_START,
 	SBI_EXT_PMU_COUNTER_STOP,
 	SBI_EXT_PMU_COUNTER_FW_READ,
+	SBI_EXT_PMU_COUNTER_FW_READ_HI,
 };
 
 union sbi_pmu_ctr_info {