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AJvYcCXJ8PPFyaESyAxZEIdj2L45kH+ZNhYnOCkbP1bZx+iOfk0aicRHb1tio6o45TZ/+Lir8wJsdBxmGxkea2cS/ed9T8bEggWDBgmrTAu4 X-Gm-Message-State: AOJu0YwaEgOa3ZJvvIadmqN42mX7jXyqKI6ME91zmydWwKhjdYLWGIH5 sjfWVohHTsb4KO25ZDpDr8QKv7Zcwo4BN27566P1TLvxmXrz9HFdC1aEUEe15XY= X-Received: by 2002:a05:6808:8b:b0:3c1:5b63:579b with SMTP id s11-20020a056808008b00b003c15b63579bmr3629169oic.49.1709103362812; Tue, 27 Feb 2024 22:56:02 -0800 (PST) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id e12-20020a62aa0c000000b006e5590729aasm1010112pff.89.2024.02.27.22.56.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Feb 2024 22:56:02 -0800 (PST) From: Samuel Holland To: Palmer Dabbelt Cc: Andrew Jones , linux-kernel@vger.kernel.org, Conor Dooley , Alexandre Ghiti , linux-riscv@lists.infradead.org, Stefan O'Rear , Samuel Holland , stable@vger.kernel.org Subject: [PATCH -fixes v4 1/3] riscv: Fix enabling cbo.zero when running in M-mode Date: Tue, 27 Feb 2024 22:55:33 -0800 Message-ID: <20240228065559.3434837-2-samuel.holland@sifive.com> X-Mailer: git-send-email 2.43.1 In-Reply-To: <20240228065559.3434837-1-samuel.holland@sifive.com> References: <20240228065559.3434837-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792124799857832796 X-GMAIL-MSGID: 1792124799857832796 When the kernel is running in M-mode, the CBZE bit must be set in the menvcfg CSR, not in senvcfg. Cc: Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode") Reviewed-by: Andrew Jones Signed-off-by: Samuel Holland Reviewed-by: Conor Dooley --- (no changes since v1) arch/riscv/include/asm/csr.h | 2 ++ arch/riscv/kernel/cpufeature.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 510014051f5d..2468c55933cd 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -424,6 +424,7 @@ # define CSR_STATUS CSR_MSTATUS # define CSR_IE CSR_MIE # define CSR_TVEC CSR_MTVEC +# define CSR_ENVCFG CSR_MENVCFG # define CSR_SCRATCH CSR_MSCRATCH # define CSR_EPC CSR_MEPC # define CSR_CAUSE CSR_MCAUSE @@ -448,6 +449,7 @@ # define CSR_STATUS CSR_SSTATUS # define CSR_IE CSR_SIE # define CSR_TVEC CSR_STVEC +# define CSR_ENVCFG CSR_SENVCFG # define CSR_SCRATCH CSR_SSCRATCH # define CSR_EPC CSR_SEPC # define CSR_CAUSE CSR_SCAUSE diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 89920f84d0a3..c5b13f7dd482 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -950,7 +950,7 @@ arch_initcall(check_unaligned_access_all_cpus); void riscv_user_isa_enable(void) { if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ)) - csr_set(CSR_SENVCFG, ENVCFG_CBZE); + csr_set(CSR_ENVCFG, ENVCFG_CBZE); } #ifdef CONFIG_RISCV_ALTERNATIVE