Message ID | 20240227232100.478238-5-pbonzini@redhat.com |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel+bounces-84198-ouuuleilei=gmail.com@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp3025515dyb; Tue, 27 Feb 2024 15:30:10 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXg8If97wRYY9ZGDPXFKVdAc0bTiVnUclBJGjEwFmMHmBeQBe7SbTi196uFoJi2Xj1QmWFYz6YbiDuA9LW+MkEfQfZOPA== X-Google-Smtp-Source: AGHT+IE9BIEnwcXe5SaIHprRlpYm3waQLYH2D7I1COjVlog7Y5H99Xf0bKskVd7Wm9fFJX+PhtFf X-Received: by 2002:a05:6a20:9c8d:b0:1a0:f713:8317 with SMTP id mj13-20020a056a209c8d00b001a0f7138317mr3864554pzb.61.1709076610094; Tue, 27 Feb 2024 15:30:10 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709076610; cv=pass; d=google.com; s=arc-20160816; b=nnk6TXPcvkKdW1rtrBM2gCKIxCPyihHaoTUszJpBOcuzi2JNmjfAJbA60+kgWJ0X9G PRx/EefJKKCK8VeCi8Ew39vv3iLLNKT5VCJBLFQAvzSYguKBNDm7KKDIUuucYwOfWHe9 1WKJonaP1TRd3APlDX+SKMV6s+LfT0e0Tywj/N2nQivhbXqbLeOn5i4LH4TUz3/O3cVf FAYsvn8Cv76kSJklNEc5CElJJMICPTo/kNFphEOjxqt9gEquaJEmC8oZ/rSiORhlyihs d9gXwe93oLJHa4Lzj2PJGCLGOxrjQluGJUWPZhG9jTl8jgpqsN/B/liMgvNN0jDVBXPg hQUA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=18Rzjsoz7zhdGFf0HyQTJYlfCD2y/TVy5xqJ/ZcFN24=; fh=w959IHqhc127FWPV0cXk2/OILEGJjMRkHPBcqMZlvxE=; b=WVdiVscBNROMUBTap8yrDNfcKChcmzPxdTxmus4yqBMidN5Tk3Rl7nJTq+H0OvhDV5 EP6yrbVnGNFAbJO3UAxrCCKCLDHi4e6XTQUdDFtuM8pU9v8F54mcDVofK3eujAhbybbB RUq/X1ydqWmCjwg7DLmOj2BXkAG08d4qqywkuLU/2Efu5FIB2VJBwKCzR/K+TVwI1TGb rmvDmdRR6cUMWUpCKhaFGZ8ghcWMIRWlXJTNbQdN4VBAbGMWjh8bmIt4aStsD7dZ7CZp 8qAQH1kGXSrPfSF6OcEoVgaPfbSOQb8bWEHIk2vn1lr3sTFySDv9swEiGQHAYKPLJg3r agyg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=ZuVlIIwR; arc=pass (i=1 spf=pass spfdomain=redhat.com dkim=pass dkdomain=redhat.com dmarc=pass fromdomain=redhat.com); spf=pass (google.com: domain of linux-kernel+bounces-84198-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-84198-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [2604:1380:45e3:2400::1]) by mx.google.com with ESMTPS id e6-20020a630f06000000b005dc9a3fa409si6108532pgl.197.2024.02.27.15.30.10 for <ouuuleilei@gmail.com> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Feb 2024 15:30:10 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-84198-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) client-ip=2604:1380:45e3:2400::1; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=ZuVlIIwR; arc=pass (i=1 spf=pass spfdomain=redhat.com dkim=pass dkdomain=redhat.com dmarc=pass fromdomain=redhat.com); spf=pass (google.com: domain of linux-kernel+bounces-84198-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-84198-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id A884328F191 for <ouuuleilei@gmail.com>; Tue, 27 Feb 2024 23:27:42 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E6EED5F483; Tue, 27 Feb 2024 23:21:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="ZuVlIIwR" Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74EB456449 for <linux-kernel@vger.kernel.org>; Tue, 27 Feb 2024 23:21:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709076071; cv=none; b=TQp+MARTqSJMFrRrp23lkK8/7BgvgHUXXamc3VhBkH5bX6z+qBCdQWvOSFa2YdeRa9gax1fW10jz9FmkZOMvqJ7E4r0PSWbL9k9m4pFH/upydyKpvzoxJGo2OI+k0G54XSOcXuva0ok/IMMvCe6NZ90jD0Db9b/dcSggT6iCSIU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709076071; c=relaxed/simple; bh=xRmVOKW+U3cJ5RX888tGYOi8yF1+QheQSC7TRhNS304=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=UnySGqZ3a8rC5T8NMHvF/77y2uAFeqkFEP5Xq+oGM8h+UVaEoXz8JaY71A03p/sKdKukV+5Ea1+KAebrqgFkJfbBI/ghVTarVrlLtYy5tMycRxp9B4u1kqSq96N8U2epyiK8f+Ow7YvX5LQc2xMLUFpSbaKpFLLjY2o643Ei7yg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=ZuVlIIwR; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1709076065; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=18Rzjsoz7zhdGFf0HyQTJYlfCD2y/TVy5xqJ/ZcFN24=; b=ZuVlIIwRpIR9osJKy0SyB6DtOGQ8yLzJNeLcnmDAuizwQ0kbr2Nxm0tTizXs/J61NsjXm2 NktVKdQlMk99FqMIvPFQVDCr/g2zWUTuMh18xnByZ2g+TFU40Fw80YsctV+9mGOljCY4kR TMa+lJ/fYjjFPmle6TJuzC1ziDDqbtQ= Received: from mimecast-mx02.redhat.com (mx-ext.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-668-XfzX3fwxMkWqYPPw3M1Kgw-1; Tue, 27 Feb 2024 18:21:02 -0500 X-MC-Unique: XfzX3fwxMkWqYPPw3M1Kgw-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id CF7803869142; Tue, 27 Feb 2024 23:21:01 +0000 (UTC) Received: from virtlab511.virt.lab.eng.bos.redhat.com (virtlab511.virt.lab.eng.bos.redhat.com [10.19.152.198]) by smtp.corp.redhat.com (Postfix) with ESMTP id 8A4C942283; Tue, 27 Feb 2024 23:21:01 +0000 (UTC) From: Paolo Bonzini <pbonzini@redhat.com> To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: seanjc@google.com, michael.roth@amd.com, isaku.yamahata@intel.com, thomas.lendacky@amd.com, Binbin Wu <binbin.wu@linux.intel.com> Subject: [PATCH 04/21] KVM: x86/mmu: Allow non-zero value for non-present SPTE and removed SPTE Date: Tue, 27 Feb 2024 18:20:43 -0500 Message-Id: <20240227232100.478238-5-pbonzini@redhat.com> In-Reply-To: <20240227232100.478238-1-pbonzini@redhat.com> References: <20240227232100.478238-1-pbonzini@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.5 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792096715725145679 X-GMAIL-MSGID: 1792096715725145679 |
Series |
TDX/SNP part 1 of n, for 6.9
|
|
Commit Message
Paolo Bonzini
Feb. 27, 2024, 11:20 p.m. UTC
From: Sean Christopherson <seanjc@google.com> For TD guest, the current way to emulate MMIO doesn't work any more, as KVM is not able to access the private memory of TD guest and do the emulation. Instead, TD guest expects to receive #VE when it accesses the MMIO and then it can explicitly make hypercall to KVM to get the expected information. To achieve this, the TDX module always enables "EPT-violation #VE" in the VMCS control. And accordingly, for the MMIO spte for the shared GPA, 1. KVM needs to set "suppress #VE" bit for the non-present SPTE so that EPT violation happens on TD accessing MMIO range. 2. On EPT violation, KVM sets the MMIO spte to clear "suppress #VE" bit so the TD guest can receive the #VE instead of EPT misconfiguration unlike VMX case. For the shared GPA that is not populated yet, EPT violation need to be triggered when TD guest accesses such shared GPA. The non-present SPTE value for shared GPA should set "suppress #VE" bit. Add "suppress #VE" bit (bit 63) to SHADOW_NONPRESENT_VALUE and REMOVED_SPTE. Unconditionally set the "suppress #VE" bit (which is bit 63) for both AMD and Intel as: 1) AMD hardware doesn't use this bit when present bit is off; 2) for normal VMX guest, KVM never enables the "EPT-violation #VE" in VMCS control and "suppress #VE" bit is ignored by hardware. Signed-off-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com> Reviewed-by: Binbin Wu <binbin.wu@linux.intel.com> Message-Id: <a99cb866897c7083430dce7f24c63b17d7121134.1705965635.git.isaku.yamahata@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> --- arch/x86/kvm/mmu/spte.h | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-)
Comments
On Tue, Feb 27, 2024 at 06:20:43PM -0500, Paolo Bonzini wrote: > From: Sean Christopherson <seanjc@google.com> > > For TD guest, the current way to emulate MMIO doesn't work any more, as KVM > is not able to access the private memory of TD guest and do the emulation. > Instead, TD guest expects to receive #VE when it accesses the MMIO and then > it can explicitly make hypercall to KVM to get the expected information. > > To achieve this, the TDX module always enables "EPT-violation #VE" in the > VMCS control. And accordingly, for the MMIO spte for the shared GPA, > 1. KVM needs to set "suppress #VE" bit for the non-present SPTE so that EPT > violation happens on TD accessing MMIO range. 2. On EPT violation, KVM > sets the MMIO spte to clear "suppress #VE" bit so the TD guest can receive > the #VE instead of EPT misconfiguration unlike VMX case. For the shared GPA > that is not populated yet, EPT violation need to be triggered when TD guest > accesses such shared GPA. The non-present SPTE value for shared GPA should > set "suppress #VE" bit. > > Add "suppress #VE" bit (bit 63) to SHADOW_NONPRESENT_VALUE and > REMOVED_SPTE. Unconditionally set the "suppress #VE" bit (which is bit 63) > for both AMD and Intel as: 1) AMD hardware doesn't use this bit when > present bit is off; 2) for normal VMX guest, KVM never enables the > "EPT-violation #VE" in VMCS control and "suppress #VE" bit is ignored by > hardware. > > Signed-off-by: Sean Christopherson <seanjc@google.com> > Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com> > Reviewed-by: Binbin Wu <binbin.wu@linux.intel.com> > Message-Id: <a99cb866897c7083430dce7f24c63b17d7121134.1705965635.git.isaku.yamahata@intel.com> > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> > --- > arch/x86/kvm/mmu/spte.h | 15 ++++++++++++++- > 1 file changed, 14 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/kvm/mmu/spte.h b/arch/x86/kvm/mmu/spte.h > index 4d1799ba2bf8..26bc95bbc962 100644 > --- a/arch/x86/kvm/mmu/spte.h > +++ b/arch/x86/kvm/mmu/spte.h > @@ -149,7 +149,20 @@ static_assert(MMIO_SPTE_GEN_LOW_BITS == 8 && MMIO_SPTE_GEN_HIGH_BITS == 11); > > #define MMIO_SPTE_GEN_MASK GENMASK_ULL(MMIO_SPTE_GEN_LOW_BITS + MMIO_SPTE_GEN_HIGH_BITS - 1, 0) > > +/* > + * Non-present SPTE value for both VMX and SVM for TDP MMU. > + * For SVM NPT, for non-present spte (bit 0 = 0), other bits are ignored. > + * For VMX EPT, bit 63 is ignored if #VE is disabled. (EPT_VIOLATION_VE=0) > + * bit 63 is #VE suppress if #VE is enabled. (EPT_VIOLATION_VE=1) > + * For TDX: > + * TDX module sets EPT_VIOLATION_VE for Secure-EPT and conventional EPT > + */ > +#ifdef CONFIG_X86_64 > +#define SHADOW_NONPRESENT_VALUE BIT_ULL(63) > +static_assert(!(SHADOW_NONPRESENT_VALUE & SPTE_MMU_PRESENT_MASK)); > +#else > #define SHADOW_NONPRESENT_VALUE 0ULL > +#endif > > extern u64 __read_mostly shadow_host_writable_mask; > extern u64 __read_mostly shadow_mmu_writable_mask; > @@ -196,7 +209,7 @@ extern u64 __read_mostly shadow_nonpresent_or_rsvd_mask; * vulnerability. Use only low bits to avoid 64-bit immediates. ^ We may remove this comment. Others are fine. Reviewed-by: Xu Yilun <yilun.xu@linux.intel.com> > * > * Only used by the TDP MMU. > */ > -#define REMOVED_SPTE 0x5a0ULL > +#define REMOVED_SPTE (SHADOW_NONPRESENT_VALUE | 0x5a0ULL) > > /* Removed SPTEs must not be misconstrued as shadow present PTEs. */ > static_assert(!(REMOVED_SPTE & SPTE_MMU_PRESENT_MASK)); > -- > 2.39.0 > > >
On 2/28/2024 7:20 AM, Paolo Bonzini wrote: > From: Sean Christopherson <seanjc@google.com> > > For TD guest, the current way to emulate MMIO doesn't work any more, as KVM > is not able to access the private memory of TD guest and do the emulation. > Instead, TD guest expects to receive #VE when it accesses the MMIO and then > it can explicitly make hypercall to KVM to get the expected information. > > To achieve this, the TDX module always enables "EPT-violation #VE" in the > VMCS control. And accordingly, for the MMIO spte for the shared GPA, > 1. KVM needs to set "suppress #VE" bit for the non-present SPTE so that EPT > violation happens on TD accessing MMIO range. 2. On EPT violation, KVM > sets the MMIO spte to clear "suppress #VE" bit so the TD guest can receive > the #VE instead of EPT misconfiguration unlike VMX case. For the shared GPA > that is not populated yet, EPT violation need to be triggered when TD guest > accesses such shared GPA. The non-present SPTE value for shared GPA should > set "suppress #VE" bit. > > Add "suppress #VE" bit (bit 63) to SHADOW_NONPRESENT_VALUE and > REMOVED_SPTE. Unconditionally set the "suppress #VE" bit (which is bit 63) > for both AMD and Intel as: 1) AMD hardware doesn't use this bit when > present bit is off; 2) for normal VMX guest, KVM never enables the > "EPT-violation #VE" in VMCS control and "suppress #VE" bit is ignored by > hardware. > > Signed-off-by: Sean Christopherson <seanjc@google.com> > Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com> > Reviewed-by: Binbin Wu <binbin.wu@linux.intel.com> > Message-Id: <a99cb866897c7083430dce7f24c63b17d7121134.1705965635.git.isaku.yamahata@intel.com> > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> + 1 to the nit pointed by Yilun, after that, Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
diff --git a/arch/x86/kvm/mmu/spte.h b/arch/x86/kvm/mmu/spte.h index 4d1799ba2bf8..26bc95bbc962 100644 --- a/arch/x86/kvm/mmu/spte.h +++ b/arch/x86/kvm/mmu/spte.h @@ -149,7 +149,20 @@ static_assert(MMIO_SPTE_GEN_LOW_BITS == 8 && MMIO_SPTE_GEN_HIGH_BITS == 11); #define MMIO_SPTE_GEN_MASK GENMASK_ULL(MMIO_SPTE_GEN_LOW_BITS + MMIO_SPTE_GEN_HIGH_BITS - 1, 0) +/* + * Non-present SPTE value for both VMX and SVM for TDP MMU. + * For SVM NPT, for non-present spte (bit 0 = 0), other bits are ignored. + * For VMX EPT, bit 63 is ignored if #VE is disabled. (EPT_VIOLATION_VE=0) + * bit 63 is #VE suppress if #VE is enabled. (EPT_VIOLATION_VE=1) + * For TDX: + * TDX module sets EPT_VIOLATION_VE for Secure-EPT and conventional EPT + */ +#ifdef CONFIG_X86_64 +#define SHADOW_NONPRESENT_VALUE BIT_ULL(63) +static_assert(!(SHADOW_NONPRESENT_VALUE & SPTE_MMU_PRESENT_MASK)); +#else #define SHADOW_NONPRESENT_VALUE 0ULL +#endif extern u64 __read_mostly shadow_host_writable_mask; extern u64 __read_mostly shadow_mmu_writable_mask; @@ -196,7 +209,7 @@ extern u64 __read_mostly shadow_nonpresent_or_rsvd_mask; * * Only used by the TDP MMU. */ -#define REMOVED_SPTE 0x5a0ULL +#define REMOVED_SPTE (SHADOW_NONPRESENT_VALUE | 0x5a0ULL) /* Removed SPTEs must not be misconstrued as shadow present PTEs. */ static_assert(!(REMOVED_SPTE & SPTE_MMU_PRESENT_MASK));