From patchwork Tue Feb 27 14:55:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 207266 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a81b:b0:108:e6aa:91d0 with SMTP id bq27csp2757276dyb; Tue, 27 Feb 2024 07:08:49 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWafOvOf6iezl6xgR+Xkxkbb67fTdDnxeV9Uux+WDRfXfq42BwlqNhdXZmzHnACWD5AUOH1w8+h0NYhgZJnnjhgOUUVaA== X-Google-Smtp-Source: AGHT+IEaHOy7f3A85ax6XVOHfVbM8QS8O0/CvVZ2L4zdkDzh6BdT05YEwEce9X2DdHChAnALTwnM X-Received: by 2002:a05:6a21:9103:b0:19e:bc8f:d0ca with SMTP id tn3-20020a056a21910300b0019ebc8fd0camr2248373pzb.58.1709046528911; Tue, 27 Feb 2024 07:08:48 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1709046528; cv=pass; d=google.com; s=arc-20160816; b=egFTdh5wbFHxJC/ULxPpO/H0BWrYeqNKwa4W4LX1n3EYxNNpKZ+y1/kL3keRbEuhhV Y5wbLSIsAzhLCXUlCNbwx9vZgTWoaToJzfLCJFGN+DY9h1SvYYO5H3/Llo502YDAH0K6 6FmefS+uF9oOeRmSgFU3ovz8ax7HTD7vTDlJeo1cmEisjxrxQ4mU7myVVMd/Rcl+tN1j Zfp+oZfgvaRNZdxCuTtggMZuRMiEHdHq7ozpn+GOAbgScHuSMnKQZFzg44F27PL6UhC1 JwfguR8cfAeI2ffJK3pGbgmlYzUyrqvxI575cMastIJnU7qYc3v7hd/0whwPk7g0w0Bc GCVA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=v1HP/zKCNKZ7DKj4WcSicb0WzfIqg8843dS/QsXReo0=; fh=x5R05joZrGxebVEAaczvDRwH1m7BAJpjuUh/Gh1YI/Y=; b=Anh1I8BQARWnvGe6cIGqiAMHtVr5pxpC/Rco9kSu+FZPGocn+Qmsc4+jT7oz1OTFoy 0GlVv7zlBNqvKCATX0DNwyhZd7wq3Yx0gWr+A8fr3kCvgfZG5jJ5xQvs5minRYQcY/9q nzAfm1P7P8aZTbnI2bwggOPFOmWtxVI1EuxVtiGLD3iG4RFaxTuYzIs4itCYPDFrDDpQ NkC2FTKARX7mtF3LInwYi3dHiphT5uxMIVBJN356rGAhlDE6NJFmS90ym8ZhW91fUse0 pgP9ObQZO8YamwQdkY3yFkluYfzJlWnORFwucpjesudASIxenq9zTfDtX6dgyp9IzHhS QpwA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=e7MTeAjB; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-83449-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-83449-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [139.178.88.99]) by mx.google.com with ESMTPS id r10-20020a632b0a000000b005dbe2220330si5584068pgr.171.2024.02.27.07.08.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Feb 2024 07:08:48 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-83449-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99; Authentication-Results: mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=e7MTeAjB; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-83449-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-83449-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id CD4BF290BB2 for ; Tue, 27 Feb 2024 14:59:42 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 540F014F966; Tue, 27 Feb 2024 14:55:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="e7MTeAjB" Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E450C149011; Tue, 27 Feb 2024 14:55:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.200 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709045745; cv=none; b=UxigakGSg78H0OClMboV7NA3tJFqZ12kbSvfzx0e7oqkqU7eBHoCaP7w4OYdXlyL6Jjg1k2uHfzx7rrVG6cJmnKCY+0ErBptkuMIdceBWU0xcxm1aquyA1qWC5MH8bkIrIxf/1RArJqK9DTPXzwcmuvNV2bUhIwRMXsF/TFeQwE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709045745; c=relaxed/simple; bh=tK4x4KGtYIXb7OTHT3sFaJe5r/9OUZNpPI5rSRlDXrg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Hp8tgVi8CBI4gBjNbi92kVPxM9TH1sFAdy8bonLQPdQ49XQOVRsHSxOiv8i4d6uNuA7pPFtPmiuqBSRRyGNjLyByzIAncjO5BwozTjsGDyrKx2bL4lHim1lfwHbG9N0F4q1aqkWr+1PQj/ZEvryrt8fcjzu1czUmyOhYlYQlcfo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=e7MTeAjB; arc=none smtp.client-ip=217.70.183.200 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Received: by mail.gandi.net (Postfix) with ESMTPSA id 3C8EF20008; Tue, 27 Feb 2024 14:55:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1709045741; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=v1HP/zKCNKZ7DKj4WcSicb0WzfIqg8843dS/QsXReo0=; b=e7MTeAjB1+3G1TvpwSyLtNIicMg452UE5OfHEWLDIzDTZ+zID8O++L9ABst8cvD99S3guv jldqfDFNoYsP81FUPLqdvMotv0/g8HgClDdv5V3xBHyJOIdUv9UhnUPN8Tj9UN6ihL4vfz dnE6aVUQxbkgDoj3cQqR3gcjb36DZ5gYo3eWPTp+GZG5uXqvYfxurhLIK+jGqCq1SWp9JR 6Hw6OxDtgqZHSWqrkKyaK6+LX/+KFne/oR2CRBL7elZU74KU4wmpa5dbrp1XouVUfhAy0z ICyNJdvgvYdrXyegfoLERZ7LxlZsLF3UVaA50q1GxGse9WXavo0wyLJ6ocA8XQ== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Tue, 27 Feb 2024 15:55:29 +0100 Subject: [PATCH v8 08/10] MIPS: mobileye: eyeq5: use OLB clocks controller node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240227-mbly-clk-v8-8-c57fbda7664a@bootlin.com> References: <20240227-mbly-clk-v8-0-c57fbda7664a@bootlin.com> In-Reply-To: <20240227-mbly-clk-v8-0-c57fbda7664a@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.13.0 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1792065172860835307 X-GMAIL-MSGID: 1792065172860835307 We add the clock controller inside the OLB syscon region and remove previous fixed devicetree nodes representing PLLs exposed by the clock controller. Signed-off-by: Théo Lebrun --- .../{eyeq5-fixed-clocks.dtsi => eyeq5-clocks.dtsi} | 54 +++++++--------------- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 11 ++++- 2 files changed, 26 insertions(+), 39 deletions(-) diff --git a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi b/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi similarity index 88% rename from arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi rename to arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi index 78f5533a95c6..aa6db704a786 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi @@ -3,42 +3,20 @@ * Copyright 2023 Mobileye Vision Technologies Ltd. */ +#include + / { /* Fixed clock */ - pll_cpu: pll-cpu { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1500000000>; - }; - - pll_vdi: pll-vdi { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1280000000>; - }; - - pll_per: pll-per { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <2000000000>; - }; - - pll_ddr0: pll-ddr0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1857210000>; - }; - - pll_ddr1: pll-ddr1 { + xtal: xtal { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <1857210000>; + clock-frequency = <30000000>; }; /* PLL_CPU derivatives */ occ_cpu: occ-cpu { compatible = "fixed-factor-clock"; - clocks = <&pll_cpu>; + clocks = <&clocks EQ5C_PLL_CPU>; #clock-cells = <0>; clock-div = <1>; clock-mult = <1>; @@ -101,7 +79,7 @@ mem_clk: mem-clk { }; occ_isram: occ-isram { compatible = "fixed-factor-clock"; - clocks = <&pll_cpu>; + clocks = <&clocks EQ5C_PLL_CPU>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; @@ -115,7 +93,7 @@ isram_clk: isram-clk { /* gate ClkRstGen_isram */ }; occ_dbu: occ-dbu { compatible = "fixed-factor-clock"; - clocks = <&pll_cpu>; + clocks = <&clocks EQ5C_PLL_CPU>; #clock-cells = <0>; clock-div = <10>; clock-mult = <1>; @@ -130,7 +108,7 @@ si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */ /* PLL_VDI derivatives */ occ_vdi: occ-vdi { compatible = "fixed-factor-clock"; - clocks = <&pll_vdi>; + clocks = <&clocks EQ5C_PLL_VDI>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; @@ -144,7 +122,7 @@ vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */ }; occ_can_ser: occ-can-ser { compatible = "fixed-factor-clock"; - clocks = <&pll_vdi>; + clocks = <&clocks EQ5C_PLL_VDI>; #clock-cells = <0>; clock-div = <16>; clock-mult = <1>; @@ -158,7 +136,7 @@ can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */ }; i2c_ser_clk: i2c-ser-clk { compatible = "fixed-factor-clock"; - clocks = <&pll_vdi>; + clocks = <&clocks EQ5C_PLL_VDI>; #clock-cells = <0>; clock-div = <20>; clock-mult = <1>; @@ -166,7 +144,7 @@ i2c_ser_clk: i2c-ser-clk { /* PLL_PER derivatives */ occ_periph: occ-periph { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&clocks EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <16>; clock-mult = <1>; @@ -225,7 +203,7 @@ gpio_clk: gpio-clk { }; emmc_sys_clk: emmc-sys-clk { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&clocks EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <10>; clock-mult = <1>; @@ -233,7 +211,7 @@ emmc_sys_clk: emmc-sys-clk { }; ccf_ctrl_clk: ccf-ctrl-clk { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&clocks EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <4>; clock-mult = <1>; @@ -241,7 +219,7 @@ ccf_ctrl_clk: ccf-ctrl-clk { }; occ_mjpeg_core: occ-mjpeg-core { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&clocks EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; @@ -265,7 +243,7 @@ mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */ }; fcmu_a_clk: fcmu-a-clk { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&clocks EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <20>; clock-mult = <1>; @@ -273,7 +251,7 @@ fcmu_a_clk: fcmu-a-clk { }; occ_pci_sys: occ-pci-sys { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&clocks EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index e82d2a57f6da..1a65b43e13b1 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -5,7 +5,7 @@ #include -#include "eyeq5-fixed-clocks.dtsi" +#include "eyeq5-clocks.dtsi" / { #address-cells = <2>; @@ -106,6 +106,15 @@ olb: system-controller@e00000 { ranges = <0x0 0x0 0xe00000 0x400>; #address-cells = <1>; #size-cells = <1>; + + clocks: clock-controller@e0002c { + compatible = "mobileye,eyeq5-clk"; + reg = <0x02c 0x50>, <0x11c 0x04>; + reg-names = "plls", "ospi"; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "ref"; + }; }; gic: interrupt-controller@140000 {