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Sat, 24 Feb 2024 07:06:26 -0800 From: To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , , , , , Subject: [PATCH v9 3/4] KVM: arm64: Set io memory s2 pte as normalnc for vfio pci device Date: Sat, 24 Feb 2024 20:35:45 +0530 Message-ID: <20240224150546.368-4-ankita@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240224150546.368-1-ankita@nvidia.com> References: <20240224150546.368-1-ankita@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D7:EE_|DS0PR12MB7678:EE_ X-MS-Office365-Filtering-Correlation-Id: a20538a6-580a-4022-9a6b-08dc354a3bbc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hC4hhayOtUyn4ffNXgDelGD9b4kuU8rkx2Zk+kuSiRA6qt6A6GVWHvEnuvbA0PdW0bkE6rCPtzu/K/FYsnRQ6BoxppPYZaKxtmeHGYxGlvzpKKGjoCVbgwKAgV4neYhozCyvl9RrZ7cO7FrWKFbke7QBt/dAbs97b0qTshqwNxh0fTuiEVc/QBbT8RwCPG9agpDz50vPxodgNGgPYpZ8miUmgwARYVdmybHHChcOo3uwk25oRpePbkIdc0QOhBqSL9YdVsVEZxq1jxwv+7SxFIxEbe0iZz3xEj9L4mylXDWav8Q78BHCaQNl5bbJvcHzJvrlGxfhg3T4LxEuCDbyj2PNzDd+1/DiTsgsWoYyaVVK878Ff6opm+pwikR6oS2QbncRU7IowTuf6UeDh2cb5gN6UA6GHsU7tN7WeJH9Gr2WFtvmM8SNMaaECj/nOHb5cEaIqz9FAaozLi0I84I3233SeYHEVrIfFHV0PRdTIBLJA56BAAN5LPYH474+/28FERNJhrnphDoXFwSLTyLOrtf9YAez2+EYDWG+vdh++tXqCRGV3nqYD/JsU85HRosohh/XdBz1NNrC02DVpMxAlbDy9IVD99K0wc8Xjns51qLS8M1uUMM+Ca7gkzPQgRBilGk9ukt6DjRn3i14rtb8ZvL87tLKu7dZSu5zheqnU6Y= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(36860700004)(40470700004)(46966006)(921011);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Feb 2024 15:06:52.3179 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a20538a6-580a-4022-9a6b-08dc354a3bbc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D7.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7678 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791793348976010340 X-GMAIL-MSGID: 1791793348976010340 From: Ankit Agrawal To provide VM with the ability to get device IO memory with NormalNC property, map device MMIO in KVM for ARM64 at stage2 as NormalNC. Having NormalNC S2 default puts guests in control (based on [1], "Combining stage 1 and stage 2 memory type attributes") of device MMIO regions memory mappings. The rules are summarized below: ([(S1) - stage1], [(S2) - stage 2]) S1 | S2 | Result NORMAL-WB | NORMAL-NC | NORMAL-NC NORMAL-WT | NORMAL-NC | NORMAL-NC NORMAL-NC | NORMAL-NC | NORMAL-NC DEVICE | NORMAL-NC | DEVICE Still this cannot be generalized to non PCI devices such as GICv2. There is insufficient information and uncertainity in the behavior of non PCI driver. A driver must indicate support using the new flag VM_ALLOW_ANY_UNCACHED. Adapt KVM to make use of the flag VM_ALLOW_ANY_UNCACHED as indicator to activate the S2 setting to NormalNc. [1] section D8.5.5 of DDI0487J_a_a-profile_architecture_reference_manual.pdf Suggested-by: Catalin Marinas Acked-by: Jason Gunthorpe Reviewed-by: Catalin Marinas Reviewed-by: Marc Zyngier Signed-off-by: Ankit Agrawal --- arch/arm64/kvm/mmu.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index d14504821b79..1742fdccb432 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -1381,7 +1381,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, int ret = 0; bool write_fault, writable, force_pte = false; bool exec_fault, mte_allowed; - bool device = false; + bool device = false, vfio_allow_any_uc = false; unsigned long mmu_seq; struct kvm *kvm = vcpu->kvm; struct kvm_mmu_memory_cache *memcache = &vcpu->arch.mmu_page_cache; @@ -1472,6 +1472,8 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, gfn = fault_ipa >> PAGE_SHIFT; mte_allowed = kvm_vma_mte_allowed(vma); + vfio_allow_any_uc = vma->vm_flags & VM_ALLOW_ANY_UNCACHED; + /* Don't use the VMA after the unlock -- it may have vanished */ vma = NULL; @@ -1557,10 +1559,14 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, if (exec_fault) prot |= KVM_PGTABLE_PROT_X; - if (device) - prot |= KVM_PGTABLE_PROT_DEVICE; - else if (cpus_have_final_cap(ARM64_HAS_CACHE_DIC)) + if (device) { + if (vfio_allow_any_uc) + prot |= KVM_PGTABLE_PROT_NORMAL_NC; + else + prot |= KVM_PGTABLE_PROT_DEVICE; + } else if (cpus_have_final_cap(ARM64_HAS_CACHE_DIC)) { prot |= KVM_PGTABLE_PROT_X; + } /* * Under the premise of getting a FSC_PERM fault, we just need to relax