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Code must establish their intent in 'x86_addr_config' and then later code will use that config information to establish the system-wide config. The L1TF wants to tweak x86_cache_bits. Let it do this, but move the code away from bugs.c so that ti can be easily called earlier en boot. Signed-off-by: Dave Hansen --- b/arch/x86/include/asm/processor.h | 6 +++++ b/arch/x86/kernel/cpu/bugs.c | 41 ------------------------------------- b/arch/x86/kernel/cpu/common.c | 2 + b/arch/x86/kernel/cpu/intel.c | 40 ++++++++++++++++++++++++++++++++++++ 4 files changed, 48 insertions(+), 41 deletions(-) diff -puN arch/x86/include/asm/processor.h~bsp-min_cache_bits arch/x86/include/asm/processor.h --- a/arch/x86/include/asm/processor.h~bsp-min_cache_bits 2024-02-22 10:09:00.220915031 -0800 +++ b/arch/x86/include/asm/processor.h 2024-02-22 10:09:00.224915188 -0800 @@ -177,6 +177,12 @@ struct x86_addr_config { * will take place at a more coarse granularity. */ u8 cache_align_mult; + + /* + * Specify a floor for the number of bits that the CPU + * caches comprehend. Used only for L1TF mitigation. + */ + u8 min_cache_bits; }; /* diff -puN arch/x86/kernel/cpu/bugs.c~bsp-min_cache_bits arch/x86/kernel/cpu/bugs.c --- a/arch/x86/kernel/cpu/bugs.c~bsp-min_cache_bits 2024-02-22 10:09:00.220915031 -0800 +++ b/arch/x86/kernel/cpu/bugs.c 2024-02-22 10:09:00.224915188 -0800 @@ -2237,45 +2237,6 @@ EXPORT_SYMBOL_GPL(l1tf_mitigation); enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); -/* - * These CPUs all support 44bits physical address space internally in the - * cache but CPUID can report a smaller number of physical address bits. - * - * The L1TF mitigation uses the top most address bit for the inversion of - * non present PTEs. When the installed memory reaches into the top most - * address bit due to memory holes, which has been observed on machines - * which report 36bits physical address bits and have 32G RAM installed, - * then the mitigation range check in l1tf_select_mitigation() triggers. - * This is a false positive because the mitigation is still possible due to - * the fact that the cache uses 44bit internally. Use the cache bits - * instead of the reported physical bits and adjust them on the affected - * machines to 44bit if the reported bits are less than 44. - */ -static void override_cache_bits(struct cpuinfo_x86 *c) -{ - if (c->x86 != 6) - return; - - switch (c->x86_model) { - case INTEL_FAM6_NEHALEM: - case INTEL_FAM6_WESTMERE: - case INTEL_FAM6_SANDYBRIDGE: - case INTEL_FAM6_IVYBRIDGE: - case INTEL_FAM6_HASWELL: - case INTEL_FAM6_HASWELL_L: - case INTEL_FAM6_HASWELL_G: - case INTEL_FAM6_BROADWELL: - case INTEL_FAM6_BROADWELL_G: - case INTEL_FAM6_SKYLAKE_L: - case INTEL_FAM6_SKYLAKE: - case INTEL_FAM6_KABYLAKE_L: - case INTEL_FAM6_KABYLAKE: - if (c->x86_cache_bits < 44) - c->x86_cache_bits = 44; - break; - } -} - static void __init l1tf_select_mitigation(void) { u64 half_pa; @@ -2288,8 +2249,6 @@ static void __init l1tf_select_mitigatio else if (cpu_mitigations_auto_nosmt()) l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; - override_cache_bits(&boot_cpu_data); - switch (l1tf_mitigation) { case L1TF_MITIGATION_OFF: case L1TF_MITIGATION_FLUSH_NOWARN: diff -puN arch/x86/kernel/cpu/common.c~bsp-min_cache_bits arch/x86/kernel/cpu/common.c --- a/arch/x86/kernel/cpu/common.c~bsp-min_cache_bits 2024-02-22 10:09:00.220915031 -0800 +++ b/arch/x86/kernel/cpu/common.c 2024-02-22 10:09:00.228915345 -0800 @@ -1139,6 +1139,8 @@ void get_cpu_address_sizes(struct cpuinf x86_config.clflush_size = detect_clflush_size(c); c->x86_cache_bits = x86_config.phys_bits; + if (c->x86_cache_bits < bsp_addr_config.min_cache_bits) + c->x86_cache_bits = bsp_addr_config.min_cache_bits; x86_config.cache_alignment = x86_clflush_size(); if (bsp_addr_config.cache_align_mult) diff -puN arch/x86/kernel/cpu/intel.c~bsp-min_cache_bits arch/x86/kernel/cpu/intel.c --- a/arch/x86/kernel/cpu/intel.c~bsp-min_cache_bits 2024-02-22 10:09:00.224915188 -0800 +++ b/arch/x86/kernel/cpu/intel.c 2024-02-22 10:09:00.228915345 -0800 @@ -395,6 +395,44 @@ detect_keyid_bits: return keyid_bits; } +/* + * These CPUs all support 44bits physical address space internally in the + * cache but CPUID can report a smaller number of physical address bits. + * + * The L1TF mitigation uses the top most address bit for the inversion of + * non present PTEs. When the installed memory reaches into the top most + * address bit due to memory holes, which has been observed on machines + * which report 36bits physical address bits and have 32G RAM installed, + * then the mitigation range check in l1tf_select_mitigation() triggers. + * This is a false positive because the mitigation is still possible due to + * the fact that the cache uses 44bit internally. Use the cache bits + * instead of the reported physical bits and adjust them on the affected + * machines to 44bit if the reported bits are less than 44. + */ +static void set_min_cache_bits(struct cpuinfo_x86 *c) +{ + if (c->x86 != 6) + return; + + switch (c->x86_model) { + case INTEL_FAM6_NEHALEM: + case INTEL_FAM6_WESTMERE: + case INTEL_FAM6_SANDYBRIDGE: + case INTEL_FAM6_IVYBRIDGE: + case INTEL_FAM6_HASWELL: + case INTEL_FAM6_HASWELL_L: + case INTEL_FAM6_HASWELL_G: + case INTEL_FAM6_BROADWELL: + case INTEL_FAM6_BROADWELL_G: + case INTEL_FAM6_SKYLAKE_L: + case INTEL_FAM6_SKYLAKE: + case INTEL_FAM6_KABYLAKE_L: + case INTEL_FAM6_KABYLAKE: + bsp_addr_config.min_cache_bits = 44; + break; + } +} + static void bsp_init_intel(struct cpuinfo_x86 *c) { int keyid_bits = 0; @@ -418,6 +456,8 @@ static void bsp_init_intel(struct cpuinf /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ if (c->x86 == 15) bsp_addr_config.cache_align_mult = 2; + + set_min_cache_bits(c); } #ifdef CONFIG_X86_32