diff mbox series

[RFC,18/34] x86/cpu/centaur: Move cache alignment override to BSP init

Message ID 20240222183950.92A959F2@davehans-spike.ostc.intel.com
State New
Headers
Series x86: Rework system-wide configuration masquerading as per-cpu data |

Commit Message

Dave Hansen Feb. 22, 2024, 6:39 p.m. UTC 
  From: Dave Hansen <dave.hansen@linux.intel.com>

The 'x86_cache_alignment' is yet another system-wide value which is stored
per-cpu.  Stop initializing it per-cpu on (some) Centaur CPUs and move it
to a new BSP init function.

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
---

 b/arch/x86/kernel/cpu/centaur.c |   15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)
diff mbox series

Patch

diff -puN arch/x86/kernel/cpu/centaur.c~centaur-c_early_init arch/x86/kernel/cpu/centaur.c
--- a/arch/x86/kernel/cpu/centaur.c~centaur-c_early_init	2024-02-22 10:08:57.268799139 -0800
+++ b/arch/x86/kernel/cpu/centaur.c	2024-02-22 10:08:57.268799139 -0800
@@ -61,12 +61,8 @@  static void init_c3(struct cpuinfo_x86 *
 	if (c->x86_model >= 6 && c->x86_model < 9)
 		set_cpu_cap(c, X86_FEATURE_3DNOW);
 #endif
-	if (c->x86 == 0x6 && c->x86_model >= 0xf) {
-		c->x86_cache_alignment = x86_clflush_size() * 2;
-		set_cpu_cap(c, X86_FEATURE_REP_GOOD);
-	}
-
-	if (c->x86 >= 7)
+	if ((c->x86 == 0x6 && c->x86_model >= 0xf) ||
+	    (c->x86 >= 7))
 		set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 }
 
@@ -217,6 +213,12 @@  static void init_centaur(struct cpuinfo_
 	init_ia32_feat_ctl(c);
 }
 
+static void bsp_init_centaur(struct cpuinfo_x86 *c)
+{
+	if (c->x86 == 0x6 && c->x86_model >= 0xf)
+		c->x86_cache_alignment = x86_clflush_size() * 2;
+}
+
 #ifdef CONFIG_X86_32
 static unsigned int
 centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
@@ -241,6 +243,7 @@  static const struct cpu_dev centaur_cpu_
 	.c_vendor	= "Centaur",
 	.c_ident	= { "CentaurHauls" },
 	.c_early_init	= early_init_centaur,
+	.c_bsp_init	= bsp_init_centaur,
 	.c_init		= init_centaur,
 #ifdef CONFIG_X86_32
 	.legacy_cache_size = centaur_size_cache,