diff mbox series

[RFC,03/34] x86/pci: Assume that clflush size is always provided

Message ID 20240222183930.18D74E8B@davehans-spike.ostc.intel.com
State New
Headers
Series x86: Rework system-wide configuration masquerading as per-cpu data |

Commit Message

Dave Hansen Feb. 22, 2024, 6:39 p.m. UTC 
  From: Dave Hansen <dave.hansen@linux.intel.com>

The early boot code always sets _some_ clflush size.  Use that fact
to avoid handling the case where it is not set.

There may have been a time when the Xen PV call in here way too
early.  But it calls get_cpu_address_sizes() before calling here
now.  It should also be safe.

Note: This series will eventually return sane defaults even very
early in boot.  I believe this is safe now, but it becomes *really*
safe later on.

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
---

 b/arch/x86/pci/common.c |   19 +++----------------
 1 file changed, 3 insertions(+), 16 deletions(-)
diff mbox series

Patch

diff -puN arch/x86/pci/common.c~x86-pci-clflush-size arch/x86/pci/common.c
--- a/arch/x86/pci/common.c~x86-pci-clflush-size	2024-02-22 10:08:49.356488521 -0800
+++ b/arch/x86/pci/common.c	2024-02-22 10:08:49.356488521 -0800
@@ -480,22 +480,9 @@  void pcibios_scan_root(int busnum)
 
 void __init pcibios_set_cache_line_size(void)
 {
-	struct cpuinfo_x86 *c = &boot_cpu_data;
-
-	/*
-	 * Set PCI cacheline size to that of the CPU if the CPU has reported it.
-	 * (For older CPUs that don't support cpuid, we se it to 32 bytes
-	 * It's also good for 386/486s (which actually have 16)
-	 * as quite a few PCI devices do not support smaller values.
-	 */
-	if (c->x86_clflush_size > 0) {
-		pci_dfl_cache_line_size = c->x86_clflush_size >> 2;
-		printk(KERN_DEBUG "PCI: pci_cache_line_size set to %d bytes\n",
-			pci_dfl_cache_line_size << 2);
-	} else {
- 		pci_dfl_cache_line_size = 32 >> 2;
-		printk(KERN_DEBUG "PCI: Unknown cacheline size. Setting to 32 bytes\n");
-	}
+	pci_dfl_cache_line_size = boot_cpu_data.x86_clflush_size >> 2;
+	printk(KERN_DEBUG "PCI: pci_cache_line_size set to %d bytes\n",
+		pci_dfl_cache_line_size << 2);
 }
 
 int __init pcibios_init(void)