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AJvYcCWJ6f82G+xqqLvDDeU/nt75HRWNg7HHBpCXMu5AK91W1588Y/hIj0mEv3cQkc9/c/pvVweoXr5IzLXjW92BQPOsGl7TSd3OLWstRkDY X-Gm-Message-State: AOJu0YzdWVIDGONKqs8IMOZuAHUP82OzaQSQDzlA+f77yKKC7vuQOvoh 0+kAhKH74AhrY4SFTz1b6naIdr+HCZVayXSjBg296Ba+sh9MhArIUr4EeiNGw1E= X-Received: by 2002:a05:6871:1ca:b0:21e:635c:a5b8 with SMTP id q10-20020a05687101ca00b0021e635ca5b8mr17215407oad.26.1708570965242; Wed, 21 Feb 2024 19:02:45 -0800 (PST) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id sk14-20020a056871800e00b0021ec89a1a2asm1937031oab.32.2024.02.21.19.02.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Feb 2024 19:02:44 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi Cc: Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Tomasz Figa , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 11/15] clk: samsung: Pass mask to wait_until_mux_stable() Date: Wed, 21 Feb 2024 21:02:31 -0600 Message-Id: <20240222030235.27815-12-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240222030235.27815-1-semen.protsenko@linaro.org> References: <20240222030235.27815-1-semen.protsenko@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791567295328061279 X-GMAIL-MSGID: 1791567295328061279 Make it possible to use wait_until_mux_stable() for MUX registers where the mask is different from MUX_MASK (e.g. in upcoming CPU clock implementation for Exynos850). No functional change. Signed-off-by: Sam Protsenko --- Changes in v2: - none drivers/clk/samsung/clk-cpu.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c index 93e961855875..89b24fd5d0a9 100644 --- a/drivers/clk/samsung/clk-cpu.c +++ b/drivers/clk/samsung/clk-cpu.c @@ -135,16 +135,16 @@ static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask) * value was changed. */ static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos, - unsigned long mux_value) + unsigned long mask, unsigned long mux_value) { unsigned long timeout = jiffies + msecs_to_jiffies(MAX_STAB_TIME); do { - if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value) + if (((readl(mux_reg) >> mux_pos) & mask) == mux_value) return; } while (time_before(jiffies, timeout)); - if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value) + if (((readl(mux_reg) >> mux_pos) & mask) == mux_value) return; pr_err("%s: re-parenting mux timed-out\n", __func__); @@ -249,7 +249,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, /* select sclk_mpll as the alternate parent */ mux_reg = readl(base + regs->mux_sel); writel(mux_reg | (1 << 16), base + regs->mux_sel); - wait_until_mux_stable(base + regs->mux_stat, 16, 2); + wait_until_mux_stable(base + regs->mux_stat, 16, MUX_MASK, 2); /* alternate parent is active now. set the dividers */ writel(div0, base + regs->div_cpu0); @@ -290,7 +290,7 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata, /* select mout_apll as the alternate parent */ mux_reg = readl(base + regs->mux_sel); writel(mux_reg & ~(1 << 16), base + regs->mux_sel); - wait_until_mux_stable(base + regs->mux_stat, 16, 1); + wait_until_mux_stable(base + regs->mux_stat, 16, MUX_MASK, 1); if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) { div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK); @@ -362,7 +362,7 @@ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, /* select the alternate parent */ mux_reg = readl(base + regs->mux_sel); writel(mux_reg | 1, base + regs->mux_sel); - wait_until_mux_stable(base + regs->mux_stat, 0, 2); + wait_until_mux_stable(base + regs->mux_stat, 0, MUX_MASK, 2); /* alternate parent is active now. set the dividers */ writel(div0, base + regs->div_cpu0); @@ -390,7 +390,7 @@ static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata, /* select apll as the alternate parent */ mux_reg = readl(base + regs->mux_sel); writel(mux_reg & ~1, base + regs->mux_sel); - wait_until_mux_stable(base + regs->mux_stat, 0, 1); + wait_until_mux_stable(base + regs->mux_stat, 0, MUX_MASK, 1); exynos_set_safe_div(cpuclk, div, div_mask); spin_unlock_irqrestore(cpuclk->lock, flags);