[net-next,v4,1/6] dt-bindings: net: hisilicon-femac-mdio: convert to YAML
Commit Message
From: Yang Xiwen <forbidden405@outlook.com>
For some FEMAC cores, MDIO bus is integrated to the MAC controller. So
We don't have a dedicated MDIO bus clock.
Also due to the PHY reset procedure, it's required to manage all clocks
and resets in the MAC controller driver. MAC controller clock can not be
shared with MDIO bus node in dts.
Mark the clock optional to resolve this problem.
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
---
.../bindings/net/hisilicon,hisi-femac-mdio.yaml | 43 ++++++++++++++++++++++
.../bindings/net/hisilicon-femac-mdio.txt | 22 -----------
2 files changed, 43 insertions(+), 22 deletions(-)
Comments
On 22/02/2024 13:43, Yang Xiwen via B4 Relay wrote:
> From: Yang Xiwen <forbidden405@outlook.com>
>
> For some FEMAC cores, MDIO bus is integrated to the MAC controller. So
> We don't have a dedicated MDIO bus clock.
Hm, this means you miss compatibles for these different cores.
>
> Also due to the PHY reset procedure, it's required to manage all clocks
> and resets in the MAC controller driver. MAC controller clock can not be
> shared with MDIO bus node in dts.
>
> Mark the clock optional to resolve this problem.
I don't understand how making clock optional solves this problem. Clock
is still there. Whether driver handles it, does not affect the binding.
Best regards,
Krzysztof
On 2/23/2024 2:14 AM, Krzysztof Kozlowski wrote:
> On 22/02/2024 13:43, Yang Xiwen via B4 Relay wrote:
>> From: Yang Xiwen <forbidden405@outlook.com>
>>
>> For some FEMAC cores, MDIO bus is integrated to the MAC controller. So
>> We don't have a dedicated MDIO bus clock.
> Hm, this means you miss compatibles for these different cores.
So you mean adding a new compatible like
"hisilicon,hisi-femac-mdio-integrated" for these ones without dedicated
clocks?
>
>> Also due to the PHY reset procedure, it's required to manage all clocks
>> and resets in the MAC controller driver. MAC controller clock can not be
>> shared with MDIO bus node in dts.
>>
>> Mark the clock optional to resolve this problem.
> I don't understand how making clock optional solves this problem. Clock
> is still there. Whether driver handles it, does not affect the binding.
>
> Best regards,
> Krzysztof
>
On 22/02/2024 19:19, Yang Xiwen wrote:
> On 2/23/2024 2:14 AM, Krzysztof Kozlowski wrote:
>> On 22/02/2024 13:43, Yang Xiwen via B4 Relay wrote:
>>> From: Yang Xiwen <forbidden405@outlook.com>
>>>
>>> For some FEMAC cores, MDIO bus is integrated to the MAC controller. So
>>> We don't have a dedicated MDIO bus clock.
>> Hm, this means you miss compatibles for these different cores.
>
>
> So you mean adding a new compatible like
> "hisilicon,hisi-femac-mdio-integrated" for these ones without dedicated
> clocks?
This is a part of a SoC, right? So compatibles should be SoC specific,
thus I expect some hisilicon,SoC-femac-mdio.
Best regards,
Krzysztof
On 2/24/2024 6:01 PM, Krzysztof Kozlowski wrote:
> On 22/02/2024 19:19, Yang Xiwen wrote:
>> On 2/23/2024 2:14 AM, Krzysztof Kozlowski wrote:
>>> On 22/02/2024 13:43, Yang Xiwen via B4 Relay wrote:
>>>> From: Yang Xiwen <forbidden405@outlook.com>
>>>>
>>>> For some FEMAC cores, MDIO bus is integrated to the MAC controller. So
>>>> We don't have a dedicated MDIO bus clock.
>>> Hm, this means you miss compatibles for these different cores.
>>
>> So you mean adding a new compatible like
>> "hisilicon,hisi-femac-mdio-integrated" for these ones without dedicated
>> clocks?
> This is a part of a SoC, right? So compatibles should be SoC specific,
> thus I expect some hisilicon,SoC-femac-mdio.
Now i'm very sure the old binding is incorrect. I've downloaded TRM for
Hi3516DV300. And found that it is, in fact, very similar to Hi3798MV200.
There is no dedicated MDIO bus clock. the MDIO bus clock is always
provided by the MAC controller. So here i can say MDIO bus is always
integrated into the FEMAC Ethernet controller, not the SoC.
Maybe someday we can merge these two drivers together later. We don't
need a MDIO bus node at all!
>
> Best regards,
> Krzysztof
>
new file mode 100644
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/hisilicon,hisi-femac-mdio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HiSilicon FEMAC MDIO bus
+
+maintainers:
+ - Yang Xiwen <forbidden405@formail.com>
+
+allOf:
+ - $ref: mdio.yaml#
+
+properties:
+ compatible:
+ const: hisilicon,hisi-femac-mdio
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mdio@10091100 {
+ compatible = "hisilicon,hisi-femac-mdio";
+ reg = <0x10091100 0x20>;
+ clocks = <&clk_mdio>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy@1 {
+ reg = <1>;
+ };
+ };
deleted file mode 100644
@@ -1,22 +0,0 @@
-Hisilicon Fast Ethernet MDIO Controller interface
-
-Required properties:
-- compatible: should be "hisilicon,hisi-femac-mdio".
-- reg: address and length of the register set for the device.
-- clocks: A phandle to the reference clock for this device.
-
-- PHY subnode: inherits from phy binding [1]
-[1] Documentation/devicetree/bindings/net/phy.txt
-
-Example:
-mdio: mdio@10091100 {
- compatible = "hisilicon,hisi-femac-mdio";
- reg = <0x10091100 0x10>;
- clocks = <&crg HI3516CV300_MDIO_CLK>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy0: phy@1 {
- reg = <1>;
- };
-};