diff mbox series

[v3,1/8] dt-bindings: clock: convert hisi-crg.txt to YAML

Message ID 20240222-clk-mv200-v3-1-f30795b50318@outlook.com
State New
Headers
Series clk: hisilicon: add support for Hi3798MV200 |

Commit Message

Yang Xiwen via B4 Relay Feb. 21, 2024, 4:41 p.m. UTC 
  From: Yang Xiwen <forbidden405@outlook.com>

Also rename to hisilicon,hisi-crg.yaml. While at it, add "syscon" and
"simple-mfd" compatibles to match the existing dts.

Add reset-controller subnode for hisilicon,hi3798cv200-crg to match the
existing hi3798cv200.dtsi.

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
---
 .../bindings/clock/hisilicon,hisi-crg.yaml         | 69 ++++++++++++++++++++++
 1 file changed, 69 insertions(+)

Comments

Krzysztof Kozlowski Feb. 22, 2024, 6:06 p.m. UTC | #1 
On 21/02/2024 17:41, Yang Xiwen via B4 Relay wrote:
> From: Yang Xiwen <forbidden405@outlook.com>
> 
> Also rename to hisilicon,hisi-crg.yaml. While at it, add "syscon" and
> "simple-mfd" compatibles to match the existing dts.
> 
> Add reset-controller subnode for hisilicon,hi3798cv200-crg to match the
> existing hi3798cv200.dtsi.
> 
> Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
> ---
>  .../bindings/clock/hisilicon,hisi-crg.yaml         | 69 ++++++++++++++++++++++

I don't see any conversion here.

Best regards,
Krzysztof
Yang Xiwen Feb. 22, 2024, 6:08 p.m. UTC | #2 
On 2/23/2024 2:06 AM, Krzysztof Kozlowski wrote:
> On 21/02/2024 17:41, Yang Xiwen via B4 Relay wrote:
>> From: Yang Xiwen <forbidden405@outlook.com>
>>
>> Also rename to hisilicon,hisi-crg.yaml. While at it, add "syscon" and
>> "simple-mfd" compatibles to match the existing dts.
>>
>> Add reset-controller subnode for hisilicon,hi3798cv200-crg to match the
>> existing hi3798cv200.dtsi.
>>
>> Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
>> ---
>>   .../bindings/clock/hisilicon,hisi-crg.yaml         | 69 ++++++++++++++++++++++
> I don't see any conversion here.


Ah. It looks like i did something wrong during rebasing. Will be more 
careful the next time.


>
> Best regards,
> Krzysztof
>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/clock/hisilicon,hisi-crg.yaml b/Documentation/devicetree/bindings/clock/hisilicon,hisi-crg.yaml
new file mode 100644
index 000000000000..2cf21cb5ff27
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/hisilicon,hisi-crg.yaml
@@ -0,0 +1,69 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/hisilicon,hisi-crg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon SOC Clock and Reset Generator (CRG) module
+
+maintainers:
+  - Yang Xiwen <forbidden405@foxmail.com>
+
+description: |
+  Hisilicon SOC clock control module which supports the clocks, resets and
+  power domains on various SoCs.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - hisilicon,hi3516cv300-crg
+          - hisilicon,hi3516cv300-sysctrl
+          - hisilicon,hi3519-crg
+          - hisilicon,hi3798cv200-crg
+          - hisilicon,hi3798cv200-sysctrl
+      - const: syscon
+      - const: simple-mfd
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 2
+    description: |
+      First cell is reset request register offset.
+      Second cell is bit offset in reset request register.
+
+  reset-controller:
+    type: object
+    description: |
+      Reset controller for Hi3798CV200 GMAC module
+
+required:
+  - compatible
+  - '#clock-cells'
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          not:
+            contains:
+              const: hisilicon,hi3798cv200-crg
+    then:
+      properties:
+        reset-controller: false
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-reset-controller@12010000 {
+        compatible = "hisilicon,hi3519-crg", "syscon", "simple-mfd";
+        reg = <0x12010000 0x10000>;
+        #clock-cells = <1>;
+        #reset-cells = <2>;
+    };