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AJvYcCVT73ZjGWandF1MlZKnBhy5KH9WSDNwzRq++nS7OXwOElbC2ZP7KqtePFqVs89c1JlvQW2MpWEojqyOAwkbXhfr7FGkJ3x/fuAp/l4Z X-Gm-Message-State: AOJu0YxQPNgbXmA3te8m9noWi5mh8cv9tpM8ibuhnPB1ml00b4M2wfK2 OTRnjAo4/W/iYYL/i5luabjbep612JNV6rChQYQvlfFHKHPJ8GHUrjPfndJTZybikpJ4A988nbA F5Z86c/WavA== X-Received: from szatan.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:2d83]) (user=panikiel job=sendgmr) by 2002:a05:600c:a383:b0:412:1500:beb4 with SMTP id hn3-20020a05600ca38300b004121500beb4mr159646wmb.7.1708531367605; Wed, 21 Feb 2024 08:02:47 -0800 (PST) Date: Wed, 21 Feb 2024 16:02:14 +0000 In-Reply-To: <20240221160215.484151-1-panikiel@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240221160215.484151-1-panikiel@google.com> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog Message-ID: <20240221160215.484151-9-panikiel@google.com> Subject: [PATCH v2 8/9] media: dt-bindings: Add Intel Displayport RX IP From: " =?utf-8?q?Pawe=C5=82_Anikiel?= " To: airlied@gmail.com, akpm@linux-foundation.org, conor+dt@kernel.org, daniel@ffwll.ch, dinguyen@kernel.org, hverkuil-cisco@xs4all.nl, krzysztof.kozlowski+dt@linaro.org, maarten.lankhorst@linux.intel.com, mchehab@kernel.org, mripard@kernel.org, robh+dt@kernel.org, tzimmermann@suse.de Cc: devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, chromeos-krk-upstreaming@google.com, ribalda@chromium.org, " =?utf-8?q?Pawe?= =?utf-8?q?=C5=82_Anikiel?= " X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791525191601724672 X-GMAIL-MSGID: 1791525191601724672 The Intel Displayport RX IP is a part of the DisplayPort Intel FPGA IP Core. It implements a DisplayPort 1.4 receiver capable of HBR3 video capture and Multi-Stream Transport. The user guide can be found here: https://www.intel.com/programmable/technical-pdfs/683273.pdf Signed-off-by: Paweł Anikiel --- .../devicetree/bindings/media/intel,dprx.yaml | 160 ++++++++++++++++++ 1 file changed, 160 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/intel,dprx.yaml diff --git a/Documentation/devicetree/bindings/media/intel,dprx.yaml b/Documentation/devicetree/bindings/media/intel,dprx.yaml new file mode 100644 index 000000000000..31025f2d5dcd --- /dev/null +++ b/Documentation/devicetree/bindings/media/intel,dprx.yaml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/intel,dprx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel DisplayPort RX IP + +maintainers: + - Paweł Anikiel + +description: | + The Intel Displayport RX IP is a part of the DisplayPort Intel FPGA IP + Core. It implements a DisplayPort 1.4 receiver capable of HBR3 video + capture and Multi-Stream Transport. + + The IP features a large number of configuration parameters, found at: + https://www.intel.com/content/www/us/en/docs/programmable/683273/23-3-20-0-1/sink-parameters.html + + The following parameters have to be enabled: + - Support DisplayPort sink + - Enable GPU control + The following parameters' values have to be set in the devicetree: + - RX maximum link rate + - Maximum lane count + - Support MST + - Max stream count (only if Support MST is enabled) + +properties: + compatible: + const: intel,dprx-20.0.1 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + intel,max-link-rate: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Max link rate configuration parameter + + intel,max-lane-count: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Max lane count configuration parameter + + intel,multi-stream-support: + type: boolean + description: Multi-Stream Transport support configuration parameter + + intel,max-stream-count: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Max stream count configuration parameter + + port: + $ref: /schemas/graph.yaml#/properties/port + description: SST main link + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: MST virtual channel 0 or SST main link + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: MST virtual channel 1 + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: MST virtual channel 2 + + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: MST virtual channel 3 + +required: + - compatible + - reg + - interrupts + +allOf: + - if: + required: + - intel,multi-stream-support + then: + required: + - intel,max-stream-count + - ports + else: + required: + - port + +additionalProperties: false + +examples: + - | + #include + + dp-receiver@c0062000 { + compatible = "intel,dprx-20.0.1"; + reg = <0xc0062000 0x800>; + interrupt-parent = <&dprx_mst_irq>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + intel,max-link-rate = <0x1e>; + intel,max-lane-count = <4>; + intel,multi-stream-support; + intel,max-stream-count = <4>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dprx_mst_0: endpoint { + remote-endpoint = <&fb_mst0_0>; + }; + }; + + port@1 { + reg = <1>; + dprx_mst_1: endpoint { + remote-endpoint = <&fb_mst1_0>; + }; + }; + + port@2 { + reg = <2>; + dprx_mst_2: endpoint { + remote-endpoint = <&fb_mst2_0>; + }; + }; + + port@3 { + reg = <3>; + dprx_mst_3: endpoint { + remote-endpoint = <&fb_mst3_0>; + }; + }; + }; + }; + + - | + dp-receiver@c0064000 { + compatible = "intel,dprx-20.0.1"; + reg = <0xc0064000 0x800>; + interrupt-parent = <&dprx_sst_irq>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + intel,max-link-rate = <0x1e>; + intel,max-lane-count = <4>; + + port { + dprx_sst_0: endpoint { + remote-endpoint = <&fb_sst_0>; + }; + }; + };