From patchwork Wed Feb 21 23:19:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 204487 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:108:e6aa:91d0 with SMTP id mn5csp1356704dyc; Wed, 21 Feb 2024 15:30:42 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWh5EXvBFNY2b/R8HU4k0SEL2zqgsi6oaIXWWXnAOger38KEW6WiKo3JclnfpBrUUsoHCr7CsMA9ZVKzExp00GtT0DrIg== X-Google-Smtp-Source: AGHT+IGp0hiA2e2G/KB8gFudTIyTJba6JzOxPqIR32vn5XDqoahLL4U2lTm5fqAlyyUtJ9bkFpkQ X-Received: by 2002:a17:902:e882:b0:1db:f95f:8891 with SMTP id w2-20020a170902e88200b001dbf95f8891mr11409096plg.11.1708558242766; Wed, 21 Feb 2024 15:30:42 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708558242; cv=pass; d=google.com; s=arc-20160816; b=HnaN9EE8MTDZFhhtxN3u57zxto9ZvAaYLEXRElXh4KmmnhvednYfyM+ifCGgIPpWbG dVDyqBl+Ppxvjju3Bq2AQY7ziioR//geZMloiNrkdDyF/tU9metEXcXM31vovo5VCBtb kParuL+1VHQpRTQSMgI9ftUgG3p4f3CFMtOSnK6cdoTI8lxtsPAu28HKFKbmVw8tlNqQ 7EnhnjONSIJrsyS6OgfKNOxY4Lh7iKrU9yL3eaBWc+JGL9uwtAniB9BHpDo40Fl4uDkq D23icfdByrgRCmxSsHN1WpOtKFPrlPioS//lDADO0UDkrMYYuydeSQZPEPSWRSpshHLu Yt3Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=2eizBs5dTICQFJ0kC5xhcBbiR4T++o8D+9i8vz7rPFY=; fh=Ph3D4iPhMs0qfrBSt7uGZnxnp3Fv4RZ3r2ELq4z6NQk=; b=AJRsyxTWpx93OtVN6rgJ8hACIG7eBC7gTM1lgji8NL56TpaUOf+sdH0Ge+UAdkBnj4 /pWZ0rXWdg3VJsuPLoMwfDlARRXgGl7RcRWh0VSquEGEcA/nytDas0LFZDlPUU0BC5ss TLxojZpccf82ndV+JYZI2mu+eMxCA7XTU52Kp8IUHF2mZ08AUJF6XQYWo969PZX/ep/t YOz3Maj6alKjaSiMdmjZGFW2wwSiHyGhgDr+5WttFQPnQkI167tL2PxX1DFbi7vkqtFe Qxy5k09bhsa6PiE6lJbewy4gznOER/g9A4Cy3oqJvi/rJ1L7VCg9hC9b+eRjleg3AVpE qS/g==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=VEzI++Ye; arc=pass (i=1 spf=pass spfdomain=quicinc.com dkim=pass dkdomain=quicinc.com dmarc=pass fromdomain=quicinc.com); spf=pass (google.com: domain of linux-kernel+bounces-75645-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-75645-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [139.178.88.99]) by mx.google.com with ESMTPS id a2-20020a170902ecc200b001db594c55b6si9274378plh.51.2024.02.21.15.30.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Feb 2024 15:30:42 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-75645-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=VEzI++Ye; arc=pass (i=1 spf=pass spfdomain=quicinc.com dkim=pass dkdomain=quicinc.com dmarc=pass fromdomain=quicinc.com); spf=pass (google.com: domain of linux-kernel+bounces-75645-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-75645-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id AAD6228741F for ; Wed, 21 Feb 2024 23:22:20 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B6B5C137C3B; Wed, 21 Feb 2024 23:19:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="VEzI++Ye" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B82FB12882D; Wed, 21 Feb 2024 23:19:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708557569; cv=none; b=iXfToCNLsJ03vISBEfklHcW/bJdypApF2X2OOCfix3tDboElcPxePVwGJ8QOHHh1uvpcXJKVyCvoYYCBC4fTgbYzG2IauGs7O7w1IIFmIxLgRSEYyiFedQr6lHdXm0WoaHSn7a8GG+6bC95zsDFleQZbZmXIIplTDXIA79xS8tg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708557569; c=relaxed/simple; bh=56OqWybgCs19IkJ49voa+SmQ1q+KscDPvV6PyQOgUok=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=LBvoKAO9zy3rYDqQYPaJsjQdTh49qdxgIKpzX4Tm1HQ9dtQlO6/bU8wF6sRdmLlcFyS9ERl5oSuVBPn9+wReUHlgbEV53ZUO0SL5KHsl3QYp2cyI5qhewcNy93prOrPCuUlSw7IMKfAhCe6Nwp3d/lenAPDp+bwrZk403pCW0mc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=VEzI++Ye; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41LNDTvZ007892; Wed, 21 Feb 2024 23:19:17 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:date:subject:mime-version:content-type :content-transfer-encoding:message-id:references:in-reply-to:to :cc; s=qcppdkim1; bh=2eizBs5dTICQFJ0kC5xhcBbiR4T++o8D+9i8vz7rPFY =; b=VEzI++Ye0Nqm3HFisHs9xKCsKQIhN25YvcdhbRo5IHWuX2lqKJzhCBhQKH8 IXcTaXAYExDhW0Zw1B7kJilfnHnX++s1RGpxNMIcKdvGW/f/lqQcERDwdp89/Qqo eqT8KDHYlJ6IqHU4Atp5CtzivsWmEOzdUONT+nLPLzRvC/CELtPTRHBnU2rfYClC keVlrpnLoBUtcc+8a1sZdWD7iJI/uVR0FaDtcwr3iOBV3MD/WRaCbzApVH9IYgCM aAqOVlwII5ahod4hrdwznmbgvmG1dszT+B79ji4890VmPTyZU38bfQgqOHmh3lXo zEjF2GBXfb5KnkgolYHjjqe5nvA== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3wdsk4r3wf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 21 Feb 2024 23:19:16 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 41LNJF9C000680 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 21 Feb 2024 23:19:16 GMT Received: from [169.254.0.1] (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 21 Feb 2024 15:19:16 -0800 From: Bjorn Andersson Date: Wed, 21 Feb 2024 15:19:17 -0800 Subject: [PATCH 9/9] arm64: defconfig: Enable sc7280 display and gpu clock controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240221-rb3gen2-dp-connector-v1-9-dc0964ef7d96@quicinc.com> References: <20240221-rb3gen2-dp-connector-v1-0-dc0964ef7d96@quicinc.com> In-Reply-To: <20240221-rb3gen2-dp-connector-v1-0-dc0964ef7d96@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , , Bjorn Andersson X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708557553; l=895; i=quic_bjorande@quicinc.com; s=20230915; h=from:subject:message-id; bh=56OqWybgCs19IkJ49voa+SmQ1q+KscDPvV6PyQOgUok=; b=J0P7RXfRDdo80b72LRdW9NBMjo9hh0HBgwaVR/ijIItqtBKAwGfuSeTUcHO2SgDZmxcia/V7V w/QyYh9VpTXBku9O6p8iCQLN0uVpDFjLKrhr1kjd3OMumT1zsDAJTTe X-Developer-Key: i=quic_bjorande@quicinc.com; a=ed25519; pk=VkhObtljigy9k0ZUIE1Mvr0Y+E1dgBEH9WoLQnUtbIM= X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: O8mQ62PEYRrxUb8ZfR3nLXDfJeB0XOgw X-Proofpoint-GUID: O8mQ62PEYRrxUb8ZfR3nLXDfJeB0XOgw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-21_09,2024-02-21_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=952 adultscore=0 impostorscore=0 clxscore=1015 bulkscore=0 phishscore=0 mlxscore=0 lowpriorityscore=0 spamscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2402210184 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791553167884799991 X-GMAIL-MSGID: 1791553167884799991 Enable the SC7280 display and gpu clock controllers to enable display support on the QCS6490 RB3gen2. Signed-off-by: Bjorn Andersson Reviewed-by: Dmitry Baryshkov --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index b8adb28185ad..193d504041dd 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1283,6 +1283,7 @@ CONFIG_QCM_DISPCC_2290=m CONFIG_QCS_GCC_404=y CONFIG_QDU_GCC_1000=y CONFIG_SC_CAMCC_8280XP=m +CONFIG_SC_DISPCC_7280=m CONFIG_SC_DISPCC_8280XP=m CONFIG_SA_GCC_8775P=y CONFIG_SA_GPUCC_8775P=m @@ -1290,6 +1291,7 @@ CONFIG_SC_GCC_7180=y CONFIG_SC_GCC_7280=y CONFIG_SC_GCC_8180X=y CONFIG_SC_GCC_8280XP=y +CONFIG_SC_GPUCC_7280=m CONFIG_SC_GPUCC_8280XP=m CONFIG_SC_LPASSCC_8280XP=m CONFIG_SDM_CAMCC_845=m