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[05/21] arm64: dts: qcom: sm8450: Add PCIe bridge node

Message ID	20240221-pcie-qcom-bridge-dts-v1-5-6c6df0f9450d@linaro.org
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel+bounces-74020-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249; From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Date: Wed, 21 Feb 2024 09:11:51 +0530 Subject: [PATCH 05/21] arm64: dts: qcom: sm8450: Add PCIe bridge node Precedence: bulk MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20240221-pcie-qcom-bridge-dts-v1-5-6c6df0f9450d@linaro.org> References: <20240221-pcie-qcom-bridge-dts-v1-0-6c6df0f9450d@linaro.org> In-Reply-To: <20240221-pcie-qcom-bridge-dts-v1-0-6c6df0f9450d@linaro.org> To: Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Series	Add PCIe bridge node in DT for Qcom SoCs \| [00/21] Add PCIe bridge node in DT for Qcom SoCs [01/21] arm64: dts: qcom: sm8250: Add PCIe bridge node [02/21] arm64: dts: qcom: sdm845: Add PCIe bridge node [03/21] arm64: dts: qcom: sm8150: Add PCIe bridge node [04/21] arm64: dts: qcom: sm8350: Add PCIe bridge node [05/21] arm64: dts: qcom: sm8450: Add PCIe bridge node [06/21] arm64: dts: qcom: sm8550: Add PCIe bridge node [07/21] arm64: dts: qcom: sm8650: Add PCIe bridge node [08/21] arm64: dts: qcom: sa8775p: Add PCIe bridge node [09/21] arm64: dts: qcom: sc8280xp: Add PCIe bridge node [10/21] arm64: dts: qcom: msm8998: Add PCIe bridge node [11/21] arm64: dts: qcom: sc7280: Add PCIe bridge node [12/21] arm64: dts: qcom: qcs404: Add PCIe bridge node [13/21] arm64: dts: qcom: sc8180x: Add PCIe bridge node [14/21] arm64: dts: qcom: msm8996: Add PCIe bridge node [15/21] arm64: dts: qcom: ipq8074: Add PCIe bridge node [16/21] arm64: dts: qcom: ipq6018: Add PCIe bridge node [17/21] ARM: dts: qcom: ipq8064: Add PCIe bridge node [18/21] ARM: dts: qcom: ipq4019: Add PCIe bridge node [19/21] ARM: dts: qcom: apq8064: Add PCIe bridge node [20/21] ARM: dts: qcom: sdx55: Add PCIe bridge node [21/21] arm64: dts: qcom: sm8650: Use "pcie" as the node name instead of "pci"

Commit Message

Manivannan Sadhasivam Feb. 21, 2024, 3:41 a.m. UTC

  On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

Comments

Neil Armstrong Feb. 21, 2024, 12:46 p.m. UTC | #1

On 21/02/2024 04:41, Manivannan Sadhasivam wrote:
> On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
> for each controller instance. Hence, add a node to represent the bridge.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
>   arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 ++++++++++++++++++++
>   1 file changed, 20 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index 01e4dfc4babd..e874cc4f8e6f 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -1824,6 +1824,16 @@ pcie0: pcie@1c00000 {
>   			pinctrl-0 = <&pcie0_default_state>;
>   
>   			status = "disabled";
> +
> +			pcie@0 {
> +				device_type = "pci";
> +				reg = <0x0 0x0 0x0 0x0 0x0>;
> +				bus-range = <0x01 0xff>;
> +
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				ranges;
> +			};
>   		};
>   
>   		pcie0_phy: phy@1c06000 {
> @@ -1931,6 +1941,16 @@ pcie1: pcie@1c08000 {
>   			pinctrl-0 = <&pcie1_default_state>;
>   
>   			status = "disabled";
> +
> +			pcie@0 {
> +				device_type = "pci";
> +				reg = <0x0 0x0 0x0 0x0 0x0>;
> +				bus-range = <0x01 0xff>;
> +
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				ranges;
> +			};
>   		};
>   
>   		pcie1_phy: phy@1c0e000 {
> 

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 01e4dfc4babd..e874cc4f8e6f 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -1824,6 +1824,16 @@  pcie0: pcie@1c00000 {
 			pinctrl-0 = <&pcie0_default_state>;
 
 			status = "disabled";
+
+			pcie@0 {
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				bus-range = <0x01 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
 		};
 
 		pcie0_phy: phy@1c06000 {
@@ -1931,6 +1941,16 @@  pcie1: pcie@1c08000 {
 			pinctrl-0 = <&pcie1_default_state>;
 
 			status = "disabled";
+
+			pcie@0 {
+				device_type = "pci";
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				bus-range = <0x01 0xff>;
+
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;
+			};
 		};
 
 		pcie1_phy: phy@1c0e000 {