diff mbox series

[3/8] dt-bindings: clock: qcom: Add SM7150 DISPCC clocks

Message ID	20240220165240.154716-4-danila@jiaxyga.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel+bounces-73410-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99; From: Danila Tikhonov <danila@jiaxyga.com> To: andersson@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, david@mainlining.org, adrian@travitia.xyz Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Danila Tikhonov <danila@jiaxyga.com> Subject: [PATCH 3/8] dt-bindings: clock: qcom: Add SM7150 DISPCC clocks Date: Tue, 20 Feb 2024 19:52:35 +0300 Message-ID: <20240220165240.154716-4-danila@jiaxyga.com> In-Reply-To: <20240220165240.154716-1-danila@jiaxyga.com> References: <20240220165240.154716-1-danila@jiaxyga.com> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Add dispcc, videocc and camcc for SM7150. \| [0/8] Add dispcc, videocc and camcc for SM7150. [1/8] dt-bindings: clock: qcom,sm7150-gcc: Add missing CX power domain [2/8] clk: qcom: gcc-sm7150: Make clk_init_data const and various fixes [3/8] dt-bindings: clock: qcom: Add SM7150 DISPCC clocks [4/8] clk: qcom: Add Display Clock Controller driver for SM7150 [5/8] dt-bindings: clock: qcom: Add SM7150 CAMCC clocks [6/8] clk: qcom: Add Camera Clock Controller driver for SM7150 [7/8] dt-bindings: clock: qcom: Add SM7150 VIDEOCC clocks [8/8] clk: qcom: Add Video Clock Controller driver for SM7150

Commit Message

Danila Tikhonov Feb. 20, 2024, 4:52 p.m. UTC

  Add device tree bindings for the display clock controller on Qualcomm
SM7150 platform.

Co-developed-by: David Wronek <david@mainlining.org>
Signed-off-by: David Wronek <david@mainlining.org>
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
---
 .../bindings/clock/qcom,sm7150-dispcc.yaml    | 75 +++++++++++++++++++
 .../dt-bindings/clock/qcom,sm7150-dispcc.h    | 59 +++++++++++++++
 2 files changed, 134 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm7150-dispcc.yaml
 create mode 100644 include/dt-bindings/clock/qcom,sm7150-dispcc.h

Comments

Rob Herring Feb. 23, 2024, 1:44 p.m. UTC | #1

On Tue, 20 Feb 2024 19:52:35 +0300, Danila Tikhonov wrote:
> Add device tree bindings for the display clock controller on Qualcomm
> SM7150 platform.
> 
> Co-developed-by: David Wronek <david@mainlining.org>
> Signed-off-by: David Wronek <david@mainlining.org>
> Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
> ---
>  .../bindings/clock/qcom,sm7150-dispcc.yaml    | 75 +++++++++++++++++++
>  .../dt-bindings/clock/qcom,sm7150-dispcc.h    | 59 +++++++++++++++
>  2 files changed, 134 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm7150-dispcc.yaml
>  create mode 100644 include/dt-bindings/clock/qcom,sm7150-dispcc.h
> 

Reviewed-by: Rob Herring <robh@kernel.org>

diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm7150-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm7150-dispcc.yaml
new file mode 100644
index 000000000000..b8d6e1d05ce2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,sm7150-dispcc.yaml
@@ -0,0 +1,75 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm7150-dispcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display Clock & Reset Controller for SM7150
+
+maintainers:
+  - Danila Tikhonov <danila@jiaxyga.com>
+  - David Wronek <david@mainlining.org>
+  - Jens Reidel <adrian@travitia.xyz>
+
+description: |
+  Qualcomm display clock control module provides the clocks, resets and power
+  domains on SM7150.
+
+  See also:: include/dt-bindings/clock/qcom,sm7150-dispcc.h
+
+properties:
+  compatible:
+    const: qcom,sm7150-dispcc
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: Board Always On XO source
+      - description: GPLL0 source from GCC
+      - description: Sleep clock source
+      - description: Byte clock from MDSS DSI PHY0
+      - description: Pixel clock from MDSS DSI PHY0
+      - description: Byte clock from MDSS DSI PHY1
+      - description: Pixel clock from MDSS DSI PHY1
+      - description: Link clock from DP PHY
+      - description: VCO DIV clock from DP PHY
+
+  power-domains:
+    maxItems: 1
+    description:
+      CX power domain.
+
+required:
+  - compatible
+  - clocks
+  - power-domains
+
+allOf:
+  - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,sm7150-gcc.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
+    clock-controller@af00000 {
+      compatible = "qcom,sm7150-dispcc";
+      reg = <0x0af00000 0x200000>;
+      clocks = <&rpmhcc RPMH_CXO_CLK>,
+               <&rpmhcc RPMH_CXO_CLK_A>,
+               <&gcc GCC_DISP_GPLL0_CLK_SRC>,
+               <&sleep_clk>,
+               <&mdss_dsi0_phy 0>,
+               <&mdss_dsi0_phy 1>,
+               <&mdss_dsi1_phy 0>,
+               <&mdss_dsi1_phy 1>,
+               <&dp_phy 0>,
+               <&dp_phy 1>;
+      power-domains = <&rpmhpd RPMHPD_CX>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+...
diff --git a/include/dt-bindings/clock/qcom,sm7150-dispcc.h b/include/dt-bindings/clock/qcom,sm7150-dispcc.h
new file mode 100644
index 000000000000..285cb3e1a375
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm7150-dispcc.h
@@ -0,0 +1,59 @@ 
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
+ * Copyright (c) 2024, David Wronek <david@mainlining.org>
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM7150_H
+#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM7150_H
+
+/* DISP_CC clock registers */
+#define DISP_CC_PLL0				0
+#define DISP_CC_MDSS_AHB_CLK			1
+#define DISP_CC_MDSS_AHB_CLK_SRC		2
+#define DISP_CC_MDSS_BYTE0_CLK			3
+#define DISP_CC_MDSS_BYTE0_CLK_SRC		4
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC		5
+#define DISP_CC_MDSS_BYTE0_INTF_CLK		6
+#define DISP_CC_MDSS_BYTE1_CLK			7
+#define DISP_CC_MDSS_BYTE1_CLK_SRC		8
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC		9
+#define DISP_CC_MDSS_BYTE1_INTF_CLK		10
+#define DISP_CC_MDSS_DP_AUX_CLK			11
+#define DISP_CC_MDSS_DP_AUX_CLK_SRC		12
+#define DISP_CC_MDSS_DP_CRYPTO_CLK		13
+#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC		14
+#define DISP_CC_MDSS_DP_LINK_CLK		15
+#define DISP_CC_MDSS_DP_LINK_CLK_SRC		16
+#define DISP_CC_MDSS_DP_LINK_INTF_CLK		17
+#define DISP_CC_MDSS_DP_PIXEL1_CLK		18
+#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC		19
+#define DISP_CC_MDSS_DP_PIXEL_CLK		20
+#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC		21
+#define DISP_CC_MDSS_ESC0_CLK			22
+#define DISP_CC_MDSS_ESC0_CLK_SRC		23
+#define DISP_CC_MDSS_ESC1_CLK			24
+#define DISP_CC_MDSS_ESC1_CLK_SRC		25
+#define DISP_CC_MDSS_MDP_CLK			26
+#define DISP_CC_MDSS_MDP_CLK_SRC		27
+#define DISP_CC_MDSS_MDP_LUT_CLK		28
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK		29
+#define DISP_CC_MDSS_PCLK0_CLK			30
+#define DISP_CC_MDSS_PCLK0_CLK_SRC		31
+#define DISP_CC_MDSS_PCLK1_CLK			32
+#define DISP_CC_MDSS_PCLK1_CLK_SRC		33
+#define DISP_CC_MDSS_ROT_CLK			34
+#define DISP_CC_MDSS_ROT_CLK_SRC		35
+#define DISP_CC_MDSS_RSCC_AHB_CLK		36
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK		37
+#define DISP_CC_MDSS_VSYNC_CLK			38
+#define DISP_CC_MDSS_VSYNC_CLK_SRC		39
+#define DISP_CC_XO_CLK_SRC			40
+#define DISP_CC_SLEEP_CLK			41
+#define DISP_CC_SLEEP_CLK_SRC			42
+
+/* DISP_CC GDSCR */
+#define MDSS_GDSC				0
+
+#endif