From patchwork Tue Feb 20 13:51:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagadeesh Kona X-Patchwork-Id: 203611 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:108:e6aa:91d0 with SMTP id mn5csp417341dyc; Tue, 20 Feb 2024 06:02:11 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUhIuh/zFeTeIP/RPW3HQ1OAQemZPZTpSpha5wle1lsJQL+ajQzJytzld4bLXgiZ7pg/uubkEbwJfnv500svEKLQx5ldA== X-Google-Smtp-Source: AGHT+IHfgJFmylet+xdtanq4IftLePn83lPfaA+jCNl6zbvkcEXq5R6fFeWDf9+K9y7lJw+OdAlb X-Received: by 2002:a05:6a20:9f49:b0:19c:7485:4f75 with SMTP id ml9-20020a056a209f4900b0019c74854f75mr21520952pzb.42.1708437731478; Tue, 20 Feb 2024 06:02:11 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708437731; cv=pass; d=google.com; s=arc-20160816; b=pKbvdQeyniIKqcuuSLfe28iwaaxfAcWkfGCaLGAhjH7m8V7xw6dae/6cIVDMIDECI+ dVdeh1rCkznWQ3jUG5eU+qI03rcvUoRvs/AmbnnbqZBWm1MnH3hqpD3xdNhaIO7zXoG9 x8sQeTjFLbd/XoYDWDwMpgQBUG1dkM3UG2dYLOAU/DL8xeQ5Mf9LMlLS3MJ7q159F18z vzN6FAXO0FJwdUjYGCQmWESS45DoLzspia9HfRSz1yfLgtXKeAXghcLJJHlRHo3P+WtN kG/6Dv7JOZG1CivPjlHPcrCWUWwO192vjr7Okp6l7owdOHhOJ4udleaPPVf3S14ESR16 32SQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=vuWUqibAXMzg7Su/NLJzChlhs1BEgYOJX0/+2EM60aE=; fh=kJvo/m4Smid3JkuHOOJdUNpEgnhk4RKfCJQbDusG808=; b=0vNyMofLTmns81JsU+nNhOBz7TbCUkKfmW0XdLvM8x31yX8+WFBx8FW3qZCTFD3WsE oTLhczf+tCqfm6cfXDZu5nCvYuF3nLEvQcd8Giahf3aoln38MLmWJcpHNXSr/nd2qh7D kUrtnpH2UiAbn9HVcvriLS5hL2OeFmm7jsY9xtQm4wunUOvQ2HJOz+rw0OXe2fLcbQBZ vj72mrNCc0lDb3t1ykqgq8XnX+aVRFoA+Gk2ktdpF0/8/wCRLs4igVCwNjDuOkRuDPu9 +sLxj5zIf3w3MUu4PSNamxcT7MlJtynpXoAvPGjqhq3U2CHx4HSuXSAjlm4Sy8vrrrqf xKyA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=oHCs1e7g; arc=pass (i=1 spf=pass spfdomain=quicinc.com dkim=pass dkdomain=quicinc.com dmarc=pass fromdomain=quicinc.com); spf=pass (google.com: domain of linux-kernel+bounces-73112-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-73112-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. [2604:1380:40f1:3f00::1]) by mx.google.com with ESMTPS id m5-20020a056a00080500b006e4799e9521si1466405pfk.13.2024.02.20.06.02.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Feb 2024 06:02:11 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-73112-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) client-ip=2604:1380:40f1:3f00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=oHCs1e7g; arc=pass (i=1 spf=pass spfdomain=quicinc.com dkim=pass dkdomain=quicinc.com dmarc=pass fromdomain=quicinc.com); spf=pass (google.com: domain of linux-kernel+bounces-73112-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-73112-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sy.mirrors.kernel.org (Postfix) with ESMTPS id BEC60B23A25 for ; Tue, 20 Feb 2024 13:54:07 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 185F56BB37; Tue, 20 Feb 2024 13:53:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="oHCs1e7g" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C25B76A8D0; Tue, 20 Feb 2024 13:53:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708437195; cv=none; b=H868kgYKlGMbE8azHpV3b7hZBDkjqnX85taOVAIzwMozPxr50PV7zbFgThHU9ry2BWIfkYeOYir3uWoyF2WppYYZftBwPJxIIHcjdfGB2Iys+fcDIuoVuLXJla2HCyhOy+1H3LyCU9Z1FuKouJTxC9Cyr8zbO9Q0U3DBoRGgxQM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708437195; c=relaxed/simple; bh=bRkOGC92iQQ86hHzU0XJ2izpjWDcLsQofM91o3QmN9M=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uUYZTUXO15tLxnu7b3XZyllxLzeydZ7P7M2VMWgSIIry+RG1CEkcQ/TF03qe+xAZc2B/P0m6C434tNWvdwyVCfanbvEUtCBM8t7Z/M9XhvyNMmc0FirtaTQPNfqMT0k5aTde0YNwYWzS5dreMDfaVBqMTpKcIZZqvsZ0ULFTaNQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=oHCs1e7g; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41KDL7Gd029299; Tue, 20 Feb 2024 13:53:08 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=vuWUqibAXMzg7Su/NLJzChlhs1BEgYOJX0/+2EM60aE=; b=oH Cs1e7gSfa8qjexWGGxM+kOxu6sLXWbFfhnz7KdE6rdIEa+V3HgELvirivxyuBZMb t9gF92uyaoO9u9Je3UU8+DO4bxiLoaNNjlxAj84EfV8ovoLy4l1h8/468SW2FXmi V6PkOLq5HwOTIZ942C1eeDtEBcS7Q+0xZMsJltPEh4gEGUxyz8JFGd3lyjQQElrk 2WE21denkHFDxR30SSKvqAMKJaE11qVsCdOa5H7FHXesnvY8lZGtOvngWWnDxWdt TOGunKELd5cRGq3y0rwsoMK+XQ0K8dWwDJ6Z2dC3YqhLjvXuVdzAFjOEcXjP66JP pbJ+AreMEyeouVobvlbA== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3wcmqp92cw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 Feb 2024 13:53:07 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 41KDr70l014576 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 20 Feb 2024 13:53:07 GMT Received: from hu-jkona-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 20 Feb 2024 05:53:01 -0800 From: Jagadeesh Kona To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley CC: Vladimir Zapolskiy , Jagadeesh Kona , Taniya Das , , , , , Ajit Pandey , Imran Shaik , "Satya Priya Kakitapalli" , Krzysztof Kozlowski Subject: [PATCH V2 1/6] dt-bindings: clock: qcom: Add SM8650 video clock controller Date: Tue, 20 Feb 2024 19:21:16 +0530 Message-ID: <20240220135121.22578-2-quic_jkona@quicinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240220135121.22578-1-quic_jkona@quicinc.com> References: <20240220135121.22578-1-quic_jkona@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: U0BOvGoIsLAVLt_snLTdFhqARHij4Taz X-Proofpoint-ORIG-GUID: U0BOvGoIsLAVLt_snLTdFhqARHij4Taz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-20_06,2024-02-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 spamscore=0 mlxlogscore=999 adultscore=0 mlxscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402200100 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791426802852322353 X-GMAIL-MSGID: 1791426802852322353 Extend device tree bindings of SM8450 videocc to add support for SM8650 videocc. While it at, fix the incorrect header include in sm8450 videocc yaml documentation. Signed-off-by: Jagadeesh Kona Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 4 +++- include/dt-bindings/clock/qcom,sm8450-videocc.h | 8 +++++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index bad8f019a8d3..79f55620eb70 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -8,18 +8,20 @@ title: Qualcomm Video Clock & Reset Controller on SM8450 maintainers: - Taniya Das + - Jagadeesh Kona description: | Qualcomm video clock control module provides the clocks, resets and power domains on SM8450. - See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h + See also:: include/dt-bindings/clock/qcom,sm8450-videocc.h properties: compatible: enum: - qcom,sm8450-videocc - qcom,sm8550-videocc + - qcom,sm8650-videocc reg: maxItems: 1 diff --git a/include/dt-bindings/clock/qcom,sm8450-videocc.h b/include/dt-bindings/clock/qcom,sm8450-videocc.h index 9d795adfe4eb..ecfebe52e4bb 100644 --- a/include/dt-bindings/clock/qcom,sm8450-videocc.h +++ b/include/dt-bindings/clock/qcom,sm8450-videocc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H @@ -19,6 +19,11 @@ #define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 9 #define VIDEO_CC_PLL0 10 #define VIDEO_CC_PLL1 11 +#define VIDEO_CC_MVS0_SHIFT_CLK 12 +#define VIDEO_CC_MVS0C_SHIFT_CLK 13 +#define VIDEO_CC_MVS1_SHIFT_CLK 14 +#define VIDEO_CC_MVS1C_SHIFT_CLK 15 +#define VIDEO_CC_XO_CLK_SRC 16 /* VIDEO_CC power domains */ #define VIDEO_CC_MVS0C_GDSC 0 @@ -34,5 +39,6 @@ #define CVP_VIDEO_CC_MVS1C_BCR 4 #define VIDEO_CC_MVS0C_CLK_ARES 5 #define VIDEO_CC_MVS1C_CLK_ARES 6 +#define VIDEO_CC_XO_CLK_ARES 7 #endif