Message ID | 20240219144015.355462-1-elder@linaro.org |
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State | New |
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[98.61.227.136]) by smtp.gmail.com with ESMTPSA id u8-20020a02b1c8000000b004741c8f34easm979144jah.56.2024.02.19.06.40.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Feb 2024 06:40:22 -0800 (PST) From: Alex Elder <elder@linaro.org> To: davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com Cc: mka@chromium.org, andersson@kernel.org, quic_cpratapa@quicinc.com, quic_avuyyuru@quicinc.com, quic_jponduru@quicinc.com, quic_subashab@quicinc.com, elder@kernel.org, netdev@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net v2] net: ipa: don't overrun IPA suspend interrupt registers Date: Mon, 19 Feb 2024 08:40:15 -0600 Message-Id: <20240219144015.355462-1-elder@linaro.org> X-Mailer: git-send-email 2.40.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791338646594231935 X-GMAIL-MSGID: 1791338646594231935 |
Series |
[net,v2] net: ipa: don't overrun IPA suspend interrupt registers
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Commit Message
Alex Elder
Feb. 19, 2024, 2:40 p.m. UTC
In newer hardware, IPA supports more than 32 endpoints. Some
registers--such as IPA interrupt registers--represent endpoints
as bits in a 4-byte register, and such registers are repeated as
needed to represent endpoints beyond the first 32.
In ipa_interrupt_suspend_clear_all(), we clear all pending IPA
suspend interrupts by reading all status register(s) and writing
corresponding registers to clear interrupt conditions.
Unfortunately the number of registers to read/write is calculated
incorrectly, and as a result we access *many* more registers than
intended. This bug occurs only when the IPA hardware signals a
SUSPEND interrupt, which happens when a packet is received for an
endpoint (or its underlying GSI channel) that is suspended. This
situation is difficult to reproduce, but possible.
Fix this by correctly computing the number of interrupt registers to
read and write. This is the only place in the code where registers
that map endpoints or channels this way perform this calculation.
Fixes: f298ba785e2d ("net: ipa: add a parameter to suspend registers")
Signed-off-by: Alex Elder <elder@linaro.org>
---
v2: Added "net" tag to the subject and rebased.
drivers/net/ipa/ipa_interrupt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Comments
Hello: This patch was applied to netdev/net.git (main) by David S. Miller <davem@davemloft.net>: On Mon, 19 Feb 2024 08:40:15 -0600 you wrote: > In newer hardware, IPA supports more than 32 endpoints. Some > registers--such as IPA interrupt registers--represent endpoints > as bits in a 4-byte register, and such registers are repeated as > needed to represent endpoints beyond the first 32. > > In ipa_interrupt_suspend_clear_all(), we clear all pending IPA > suspend interrupts by reading all status register(s) and writing > corresponding registers to clear interrupt conditions. > > [...] Here is the summary with links: - [net,v2] net: ipa: don't overrun IPA suspend interrupt registers https://git.kernel.org/netdev/net/c/d80f8e96d47d You are awesome, thank you!
diff --git a/drivers/net/ipa/ipa_interrupt.c b/drivers/net/ipa/ipa_interrupt.c index 4bc05948f772d..a78c692f2d3c5 100644 --- a/drivers/net/ipa/ipa_interrupt.c +++ b/drivers/net/ipa/ipa_interrupt.c @@ -212,7 +212,7 @@ void ipa_interrupt_suspend_clear_all(struct ipa_interrupt *interrupt) u32 unit_count; u32 unit; - unit_count = roundup(ipa->endpoint_count, 32); + unit_count = DIV_ROUND_UP(ipa->endpoint_count, 32); for (unit = 0; unit < unit_count; unit++) { const struct reg *reg; u32 val;