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d=ew.tq-group.com; s=dkim; t=1708345498; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=ih/v3JlPgjnunjeMXetvHkaR0ZTTwffvOCV3Ri/27Bg=; b=J2+oV1ZKOKLcn/qz2bJ4YrrX7urblOuYeRkmuWrGrDbzdB83S6EHxLju7VhlxI1o9gdH4P gOPTG5kfX1mapEHgwI8olPJSvd6Sa8WK+dLdHrcsR4q1ZPV4ufqTOyRTH4F/2Fc7bBGOtp mI+xwz2RrdckbZnKGrEnvt99ogvYyCo/e9XZYaHDKlmkXFtvDbWn3gdKnr7J3LmD3tfyq9 /5J2Ntk5yfaIdHw3vH/gxNUBr+G+1I7A88E6eom7g6dsY1DzEVdHekMeyS7jtj2NHDeYGZ IESZMabRoKToR7tODX+CySpQCeTl4bWR9MQVyqyMFQOglcj+IK+omsmIptYlFg== From: Alexander Stein To: Stefan Agner , Alison Wang , David Airlie , Daniel Vetter , Matthias Schiffer Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Alexander Stein Subject: [RESEND 2/2] drm: fsl-dcu: enable PIXCLK on LS1021A Date: Mon, 19 Feb 2024 13:24:49 +0100 Message-Id: <20240219122449.3083748-2-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240219122449.3083748-1-alexander.stein@ew.tq-group.com> References: <20240219122449.3083748-1-alexander.stein@ew.tq-group.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791330165246278479 X-GMAIL-MSGID: 1791330165246278479 From: Matthias Schiffer The PIXCLK needs to be enabled in SCFG before accessing certain DCU registers, or the access will hang. Signed-off-by: Matthias Schiffer Signed-off-by: Alexander Stein --- drivers/gpu/drm/fsl-dcu/Kconfig | 1 + drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 14 ++++++++++++++ drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h | 3 +++ 3 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/fsl-dcu/Kconfig b/drivers/gpu/drm/fsl-dcu/Kconfig index 5ca71ef87325..c9ee98693b48 100644 --- a/drivers/gpu/drm/fsl-dcu/Kconfig +++ b/drivers/gpu/drm/fsl-dcu/Kconfig @@ -8,6 +8,7 @@ config DRM_FSL_DCU select DRM_PANEL select REGMAP_MMIO select VIDEOMODE_HELPERS + select MFD_SYSCON if SOC_LS1021A help Choose this option if you have an Freescale DCU chipset. If M is selected the module will be called fsl-dcu-drm. diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c index 90cbd18f096d..283858350961 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c @@ -100,12 +100,26 @@ static void fsl_dcu_irq_uninstall(struct drm_device *dev) static int fsl_dcu_load(struct drm_device *dev, unsigned long flags) { struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; + struct regmap *scfg; int ret; ret = fsl_dcu_drm_modeset_init(fsl_dev); if (ret < 0) return dev_err_probe(dev->dev, ret, "failed to initialize mode setting\n"); + scfg = syscon_regmap_lookup_by_compatible("fsl,ls1021a-scfg"); + if (PTR_ERR(scfg) != -ENODEV) { + /* + * For simplicity, enable the PIXCLK unconditionally. Disabling + * the clock in PM or on unload could be implemented as a future + * improvement. + */ + ret = regmap_update_bits(scfg, SCFG_PIXCLKCR, SCFG_PIXCLKCR_PXCEN, + SCFG_PIXCLKCR_PXCEN); + if (ret < 0) + return dev_err_probe(dev->dev, ret, "failed to enable pixclk\n"); + } + ret = drm_vblank_init(dev, dev->mode_config.num_crtc); if (ret < 0) { dev_err(dev->dev, "failed to initialize vblank\n"); diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h index e2049a0e8a92..566396013c04 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h @@ -160,6 +160,9 @@ #define FSL_DCU_ARGB4444 12 #define FSL_DCU_YUV422 14 +#define SCFG_PIXCLKCR 0x28 +#define SCFG_PIXCLKCR_PXCEN BIT(31) + #define VF610_LAYER_REG_NUM 9 #define LS1021A_LAYER_REG_NUM 10