Message ID | 20240219-topic-rb1_gpu-v2-4-2d3d6a0db040@linaro.org |
---|---|
State | New |
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[78.88.45.141]) by smtp.gmail.com with ESMTPSA id mj8-20020a170906af8800b00a3ee9305b02sm4091226ejb.20.2024.02.23.13.21.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Feb 2024 13:21:55 -0800 (PST) From: Konrad Dybcio <konrad.dybcio@linaro.org> Date: Fri, 23 Feb 2024 22:21:40 +0100 Subject: [PATCH v2 4/7] drm/msm/adreno: Add missing defines for A702 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: <linux-kernel.vger.kernel.org> List-Subscribe: <mailto:linux-kernel+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-kernel+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20240219-topic-rb1_gpu-v2-4-2d3d6a0db040@linaro.org> References: <20240219-topic-rb1_gpu-v2-0-2d3d6a0db040@linaro.org> In-Reply-To: <20240219-topic-rb1_gpu-v2-0-2d3d6a0db040@linaro.org> To: Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>, Joerg Roedel <joro@8bytes.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Bjorn Andersson <andersson@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Clark <robdclark@gmail.com>, Abhinav Kumar <quic_abhinavk@quicinc.com>, Dmitry Baryshkov <dmitry.baryshkov@linaro.org>, Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch> Cc: Marijn Suijten <marijn.suijten@somainline.org>, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio <konradybcio@kernel.org>, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio <konrad.dybcio@linaro.org> X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708723303; l=1379; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=2VUaTHaFXwk9sVr7gsAachnQpNO5KMem0UoFA2HST7g=; b=NXYDavFJ3TC/4KiU+OLYy06EnXZgFmyjLCFX7iZKoUTbin8UI3o1WKHxiAxISRJ/Lpa8whlgL OmvgcvRyQ93Bgd7cMUYUQkgAXoezpOmzuvOSNtRIQf2InPOAkx5rZ92 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791726348620898837 X-GMAIL-MSGID: 1791726348620898837 |
Series |
A702 support
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Commit Message
Konrad Dybcio
Feb. 23, 2024, 9:21 p.m. UTC
Add some defines required for A702. Can be substituted with a header
sync after merging mesa!27665 [1].
[1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27665
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
Comments
On Fri, 23 Feb 2024 at 23:21, Konrad Dybcio <konrad.dybcio@linaro.org> wrote: > > Add some defines required for A702. Can be substituted with a header > sync after merging mesa!27665 [1]. > > [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27665 > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > drivers/gpu/drm/msm/adreno/a6xx.xml.h | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h index 863b5e3b0e67..1ec4dbc0e746 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h @@ -1945,6 +1945,24 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00 #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122 +#define REG_A6XX_RBBM_CLOCK_CNTL_FCHE 0x00000123 + +#define REG_A6XX_RBBM_CLOCK_DELAY_FCHE 0x00000124 + +#define REG_A6XX_RBBM_CLOCK_HYST_FCHE 0x00000125 + +#define REG_A6XX_RBBM_CLOCK_CNTL_MHUB 0x00000126 + +#define REG_A6XX_RBBM_CLOCK_DELAY_MHUB 0x00000127 + +#define REG_A6XX_RBBM_CLOCK_HYST_MHUB 0x00000128 + +#define REG_A6XX_RBBM_CLOCK_DELAY_GLC 0x00000129 + +#define REG_A6XX_RBBM_CLOCK_HYST_GLC 0x0000012a + +#define REG_A6XX_RBBM_CLOCK_CNTL_GLC 0x0000012b + #define REG_A7XX_RBBM_CLOCK_HYST2_VFD 0x0000012f #define REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL 0x000005ff