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Sun, 18 Feb 2024 09:40:34 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Sun, 18 Feb 2024 17:40:30 +0800 Subject: [PATCH 1/2] arm64: dts: hi3798cv200: Fix the size of GICR Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240218-cache-v1-1-2c0a8a4472e7@outlook.com> References: <20240218-cache-v1-0-2c0a8a4472e7@outlook.com> In-Reply-To: <20240218-cache-v1-0-2c0a8a4472e7@outlook.com> To: Wei Xu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Alex Elder , Peter Griffin Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708249233; l=1243; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=cM/+jwZOd1PTjdjnQjIchbxxptzvx3CBS8/AnT/3vpc=; b=/A9JI75VcknvkbU5W9gkLRmoqf1WJh/ohHjKqGbIMBsKkkK/WPK5yfIjww3AcQbSkUzL8JDSV NrPoGdyLs04AXuPMwP/6CSlzS2G1hIP7BvdWXE43WyHj2CAK/4lqJ+l X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen Reply-To: X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791229186952291280 X-GMAIL-MSGID: 1791229186952291280 From: Yang Xiwen During boot, kernel complains: [ 0.000000] GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set Looking at GIC-400 datasheet, I believe this SoC is using a regular GIC-400 and the GICR space size should be 8 KB rather than 256B. With this patch: [ 0.000000] GIC: Using split EOI/Deactivate mode So this should be the correct fix. Fixes: 2f20182ed670 ("arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board") Signed-off-by: Yang Xiwen --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index ed1b5a7a6067..d01023401d7e 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -58,7 +58,7 @@ cpu@3 { gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ - <0x0 0xf1002000 0x0 0x100>; /* GICC */ + <0x0 0xf1002000 0x0 0x2000>; /* GICC */ #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller;