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AJvYcCWd/pjl3DRP2WlHCgaAWW4ItbK4JOs28b/CDz/gktVbZrmvODgcCkF8FbBUgIHyT68dTCEqZRAUw82hcfoV6CQ5Poz96IYweQQbW7Is X-Gm-Message-State: AOJu0Yyc84wqbfCi/+MGOPn/q/MKtX+STegHv+Xq89LX09mns9CsXOM5 HyTvhBYKlZdMsYUo+M+6ebrozu1WOTV7exQvhdRpVtaqDcZJSfTBoNjX8h9Yq8EMhCamnQScMyv ZRQUU2ccz8Z77r4lzAQ== X-Received: from ericchancf.c.googlers.com ([fda3:e722:ac3:cc00:4f:4b78:c0a8:4139]) (user=ericchancf job=sendgmr) by 2002:a05:6902:2284:b0:dc8:5e26:f4d7 with SMTP id dn4-20020a056902228400b00dc85e26f4d7mr1779458ybb.13.1708175574920; Sat, 17 Feb 2024 05:12:54 -0800 (PST) Date: Sat, 17 Feb 2024 13:12:49 +0000 In-Reply-To: <20240217131206.3667544-1-ericchancf@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240217131206.3667544-1-ericchancf@google.com> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog Message-ID: <20240217131249.3668103-1-ericchancf@google.com> Subject: [PATCH v6 1/4] riscv/barrier: Define __{mb,rmb,wmb} From: Eric Chan To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, ericchancf@google.com, conor.dooley@microchip.com, parri.andrea@gmail.com, emil.renner.berthing@canonical.com, samuel.holland@sifive.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791151929471839805 X-GMAIL-MSGID: 1791151929471839805 Introduce __{mb,rmb,wmb}, and rely on the generic definitions for {mb,rmb,wmb}. Although KCSAN is not supported yet, the definitions can be made more consistent with generic instrumentation. Also add a space to make the changes pass check by checkpatch.pl. Without the space, the error message is as below: ERROR: space required after that ',' (ctx:VxV) 26: FILE: arch/riscv/include/asm/barrier.h:23: +#define __mb() RISCV_FENCE(iorw,iorw) ^ Signed-off-by: Eric Chan --- v5 -> v6: let this change to pass review by checkpatch.pl instead of overwriting again in [PATCH 4/4] v3 -> v4: fix commit message weird line breaks arch/riscv/include/asm/barrier.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.44.0.rc0.258.g7320e95886-goog diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 110752594228..173b44a989f8 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -20,9 +20,9 @@ __asm__ __volatile__ ("fence " #p "," #s : : : "memory") /* These barriers need to enforce ordering on both devices or memory. */ -#define mb() RISCV_FENCE(iorw,iorw) -#define rmb() RISCV_FENCE(ir,ir) -#define wmb() RISCV_FENCE(ow,ow) +#define __mb() RISCV_FENCE(iorw, iorw) +#define __rmb() RISCV_FENCE(ir, ir) +#define __wmb() RISCV_FENCE(ow, ow) /* These barriers do not need to enforce ordering on devices, just memory. */ #define __smp_mb() RISCV_FENCE(rw,rw)