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Sat, 17 Feb 2024 14:02:51 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Sat, 17 Feb 2024 22:02:47 +0800 Subject: [PATCH RFC v2 3/4] phy: hisilicon: hisi-inno-phy: add support for Hi3798MV200 INNO PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240217-inno-phy-v2-3-3bf7e87b0e9e@outlook.com> References: <20240217-inno-phy-v2-0-3bf7e87b0e9e@outlook.com> In-Reply-To: <20240217-inno-phy-v2-0-3bf7e87b0e9e@outlook.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Shawn Guo , Philipp Zabel Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kishon Vijay Abraham I , David Yang , Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708178566; l=4896; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=GrCYJatgoRWu7Bx47GQoBXbcdNOq+uSu0U+veti+reE=; b=io0SbJNsSxMgQ3OaTc/0Z9tbTMuoUOoI7sFB5VfjG/ciOZl7aRIc2R0BYahKWoutI+NCTpO1B 377gjmMHMKGC9NMcLg0mt9uEo6KkEz1OM3+1O/B+KLbzoqsmWc1xz3t X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen Reply-To: X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791155129521873131 X-GMAIL-MSGID: 1791155129521873131 From: Yang Xiwen Direct MMIO resgiter access is used by Hi3798MV200. For other models, of_iomap() returns 0 due to insufficient length. So they are unaffected. Also Hi3798MV200 INNO PHY has an extra reset required to be deasserted, switch to reset_control_bulk_() APIs to resolve this. Signed-off-by: Yang Xiwen --- drivers/phy/hisilicon/phy-hisi-inno-usb2.c | 65 ++++++++++++++++++------------ 1 file changed, 39 insertions(+), 26 deletions(-) diff --git a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c index b7e740eb4752..5175e5a351ac 100644 --- a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c +++ b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -43,6 +44,7 @@ #define PHY_CLK_ENABLE BIT(2) struct hisi_inno_phy_port { + void __iomem *base; struct reset_control *utmi_rst; struct hisi_inno_phy_priv *priv; }; @@ -50,7 +52,7 @@ struct hisi_inno_phy_port { struct hisi_inno_phy_priv { void __iomem *mmio; struct clk *ref_clk; - struct reset_control *por_rst; + struct reset_control *rsts; unsigned int type; struct hisi_inno_phy_port ports[INNO_PHY_PORT_NUM]; }; @@ -62,26 +64,31 @@ static void hisi_inno_phy_write_reg(struct hisi_inno_phy_priv *priv, u32 val; u32 value; - if (priv->type == PHY_TYPE_0) - val = (data & PHY_TEST_DATA) | - ((addr << PHY_TEST_ADDR_OFFSET) & PHY0_TEST_ADDR) | - ((port << PHY0_TEST_PORT_OFFSET) & PHY0_TEST_PORT) | - PHY0_TEST_WREN | PHY0_TEST_RST; - else - val = (data & PHY_TEST_DATA) | - ((addr << PHY_TEST_ADDR_OFFSET) & PHY1_TEST_ADDR) | - ((port << PHY1_TEST_PORT_OFFSET) & PHY1_TEST_PORT) | - PHY1_TEST_WREN | PHY1_TEST_RST; - writel(val, reg); - - value = val; - if (priv->type == PHY_TYPE_0) - value |= PHY0_TEST_CLK; - else - value |= PHY1_TEST_CLK; - writel(value, reg); - - writel(val, reg); + if (priv->ports[port].base) + // stride is 4 + writel(data, (u32 *)priv->ports[port].base + addr); + else { + if (priv->type == PHY_TYPE_0) + val = (data & PHY_TEST_DATA) | + ((addr << PHY_TEST_ADDR_OFFSET) & PHY0_TEST_ADDR) | + ((port << PHY0_TEST_PORT_OFFSET) & PHY0_TEST_PORT) | + PHY0_TEST_WREN | PHY0_TEST_RST; + else + val = (data & PHY_TEST_DATA) | + ((addr << PHY_TEST_ADDR_OFFSET) & PHY1_TEST_ADDR) | + ((port << PHY1_TEST_PORT_OFFSET) & PHY1_TEST_PORT) | + PHY1_TEST_WREN | PHY1_TEST_RST; + writel(val, reg); + + value = val; + if (priv->type == PHY_TYPE_0) + value |= PHY0_TEST_CLK; + else + value |= PHY1_TEST_CLK; + writel(value, reg); + + writel(val, reg); + } } static void hisi_inno_phy_setup(struct hisi_inno_phy_priv *priv) @@ -104,7 +111,7 @@ static int hisi_inno_phy_init(struct phy *phy) return ret; udelay(REF_CLK_STABLE_TIME); - reset_control_deassert(priv->por_rst); + reset_control_deassert(priv->rsts); udelay(POR_RST_COMPLETE_TIME); /* Set up phy registers */ @@ -122,7 +129,7 @@ static int hisi_inno_phy_exit(struct phy *phy) struct hisi_inno_phy_priv *priv = port->priv; reset_control_assert(port->utmi_rst); - reset_control_assert(priv->por_rst); + reset_control_assert(priv->rsts); clk_disable_unprepare(priv->ref_clk); return 0; @@ -158,15 +165,16 @@ static int hisi_inno_phy_probe(struct platform_device *pdev) if (IS_ERR(priv->ref_clk)) return PTR_ERR(priv->ref_clk); - priv->por_rst = devm_reset_control_get_exclusive(dev, NULL); - if (IS_ERR(priv->por_rst)) - return PTR_ERR(priv->por_rst); + priv->rsts = devm_reset_control_array_get(dev, false, false); + if (IS_ERR(priv->rsts)) + return PTR_ERR(priv->rsts); priv->type = (uintptr_t) of_device_get_match_data(dev); for_each_child_of_node(np, child) { struct reset_control *rst; struct phy *phy; + void __iomem *base; rst = of_reset_control_get_exclusive(child, NULL); if (IS_ERR(rst)) { @@ -174,7 +182,10 @@ static int hisi_inno_phy_probe(struct platform_device *pdev) return PTR_ERR(rst); } + base = of_iomap(child, 0); + priv->ports[i].utmi_rst = rst; + priv->ports[i].base = base; priv->ports[i].priv = priv; phy = devm_phy_create(dev, child, &hisi_inno_phy_ops); @@ -205,6 +216,8 @@ static const struct of_device_id hisi_inno_phy_of_match[] = { .data = (void *) PHY_TYPE_0 }, { .compatible = "hisilicon,hi3798mv100-usb2-phy", .data = (void *) PHY_TYPE_1 }, + { .compatible = "hisilicon,hi3798mv200-usb2-phy", + .data = (void *) PHY_TYPE_0 }, { }, }; MODULE_DEVICE_TABLE(of, hisi_inno_phy_of_match);