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AJvYcCUvkAj6KV9EcwfoU8t0PJmZGLnEfTdZOp6ROWau78NEoZlFiO42DEEqOSpkEhOFiEUvsTk+zkUtkArmXdG6tz6/bX0/Imbw5N57/nGm X-Gm-Message-State: AOJu0YyfNO4cER6+lfe/cq6qYlk4qztN57+EKZ2t9erqwcpz139WYX4/ qzedURPvBcOXJHF+ZGiiGaPKE7MzQ1abmzipAvo3p5+WsQmtG17o/1ORBDGAUTw= X-Received: by 2002:a05:6870:8192:b0:21e:6672:a46f with SMTP id k18-20020a056870819200b0021e6672a46fmr3255262oae.29.1708122775911; Fri, 16 Feb 2024 14:32:55 -0800 (PST) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id ov11-20020a056870cb8b00b0021e70d17dc7sm199912oab.30.2024.02.16.14.32.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 14:32:55 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi Cc: Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Tomasz Figa , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 12/16] clk: samsung: Pass mask to wait_until_mux_stable() Date: Fri, 16 Feb 2024 16:32:41 -0600 Message-Id: <20240216223245.12273-13-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240216223245.12273-1-semen.protsenko@linaro.org> References: <20240216223245.12273-1-semen.protsenko@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791096794041691607 X-GMAIL-MSGID: 1791096794041691607 Make it possible to use wait_until_mux_stable() for MUX registers where the mask is different from MUX_MASK (e.g. in upcoming CPU clock implementation for Exynos850). No functional change. Signed-off-by: Sam Protsenko --- drivers/clk/samsung/clk-cpu.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c index 744b609c222d..5ea618da0bc1 100644 --- a/drivers/clk/samsung/clk-cpu.c +++ b/drivers/clk/samsung/clk-cpu.c @@ -134,16 +134,16 @@ static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask) * value was changed. */ static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos, - unsigned long mux_value) + unsigned long mask, unsigned long mux_value) { unsigned long timeout = jiffies + msecs_to_jiffies(MAX_STAB_TIME); do { - if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value) + if (((readl(mux_reg) >> mux_pos) & mask) == mux_value) return; } while (time_before(jiffies, timeout)); - if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value) + if (((readl(mux_reg) >> mux_pos) & mask) == mux_value) return; pr_err("%s: re-parenting mux timed-out\n", __func__); @@ -248,7 +248,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, /* select sclk_mpll as the alternate parent */ mux_reg = readl(base + regs->mux_sel); writel(mux_reg | (1 << 16), base + regs->mux_sel); - wait_until_mux_stable(base + regs->mux_stat, 16, 2); + wait_until_mux_stable(base + regs->mux_stat, 16, MUX_MASK, 2); /* alternate parent is active now. set the dividers */ writel(div0, base + regs->div_cpu0); @@ -289,7 +289,7 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata, /* select mout_apll as the alternate parent */ mux_reg = readl(base + regs->mux_sel); writel(mux_reg & ~(1 << 16), base + regs->mux_sel); - wait_until_mux_stable(base + regs->mux_stat, 16, 1); + wait_until_mux_stable(base + regs->mux_stat, 16, MUX_MASK, 1); if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) { div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK); @@ -361,7 +361,7 @@ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, /* select the alternate parent */ mux_reg = readl(base + regs->mux_sel); writel(mux_reg | 1, base + regs->mux_sel); - wait_until_mux_stable(base + regs->mux_stat, 0, 2); + wait_until_mux_stable(base + regs->mux_stat, 0, MUX_MASK, 2); /* alternate parent is active now. set the dividers */ writel(div0, base + regs->div_cpu0); @@ -389,7 +389,7 @@ static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata, /* select apll as the alternate parent */ mux_reg = readl(base + regs->mux_sel); writel(mux_reg & ~1, base + regs->mux_sel); - wait_until_mux_stable(base + regs->mux_stat, 0, 1); + wait_until_mux_stable(base + regs->mux_stat, 0, MUX_MASK, 1); exynos_set_safe_div(cpuclk, div, div_mask); spin_unlock_irqrestore(cpuclk->lock, flags);