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AJvYcCWFb/rEJN2VyvQclj3yPzUaO2WsChMdNCNipG9bUzgQ0xYu84gn9cbe90SZhYj2sDI6OAJAfc5Uq4aYFDirjy3eRSakq+24pGtsSayI X-Gm-Message-State: AOJu0YzriN47qW9pjdo+FkVrGTPEi/MOyJ8sUbs018/8IR5kI6YxQY/6 Sxr3WWdz4ouoV7YpBap3PIhCpwGEgTxs320FWZ/HDgDw7hFnQ9n37xwZazjP59fhQd//IvA0dyI 7 X-Received: by 2002:a4a:345e:0:b0:59c:b57a:5746 with SMTP id n30-20020a4a345e000000b0059cb57a5746mr6347301oof.4.1708122773428; Fri, 16 Feb 2024 14:32:53 -0800 (PST) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id b6-20020a4ad886000000b0059fae73df22sm112897oov.3.2024.02.16.14.32.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Feb 2024 14:32:53 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi Cc: Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Tomasz Figa , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/16] clk: samsung: Pass register layout type explicitly to CLK_CPU() Date: Fri, 16 Feb 2024 16:32:38 -0600 Message-Id: <20240216223245.12273-10-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240216223245.12273-1-semen.protsenko@linaro.org> References: <20240216223245.12273-1-semen.protsenko@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791098283231366964 X-GMAIL-MSGID: 1791098283231366964 Make it more obvious which register layout should be used for a CPU clock. It prepares clk-cpu.c for adding new chips support. No functional change. Signed-off-by: Sam Protsenko --- drivers/clk/samsung/clk-cpu.c | 2 +- drivers/clk/samsung/clk-cpu.h | 12 ++++++++++-- drivers/clk/samsung/clk-exynos3250.c | 2 +- drivers/clk/samsung/clk-exynos4.c | 6 +++--- drivers/clk/samsung/clk-exynos5250.c | 3 ++- drivers/clk/samsung/clk-exynos5420.c | 8 ++++---- drivers/clk/samsung/clk-exynos5433.c | 8 ++++---- drivers/clk/samsung/clk.h | 4 +++- 8 files changed, 28 insertions(+), 17 deletions(-) diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c index 4c46416281a3..21998c89b96d 100644 --- a/drivers/clk/samsung/clk-cpu.c +++ b/drivers/clk/samsung/clk-cpu.c @@ -464,7 +464,7 @@ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, cpuclk->lock = &ctx->lock; cpuclk->flags = clk_data->flags; cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb; - if (clk_data->flags & CLK_CPU_HAS_E5433_REGS_LAYOUT) { + if (clk_data->reg_layout == CPUCLK_LAYOUT_E5433) { cpuclk->pre_rate_cb = exynos5433_cpuclk_pre_rate_change; cpuclk->post_rate_cb = exynos5433_cpuclk_post_rate_change; } else { diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h index ee57f3638fed..4382ab005ad3 100644 --- a/drivers/clk/samsung/clk-cpu.h +++ b/drivers/clk/samsung/clk-cpu.h @@ -12,8 +12,16 @@ #define CLK_CPU_HAS_DIV1 BIT(0) /* When ALT parent is active, debug clocks need safe divider values */ #define CLK_CPU_NEEDS_DEBUG_ALT_DIV BIT(1) -/* The CPU clock registers have Exynos5433-compatible layout */ -#define CLK_CPU_HAS_E5433_REGS_LAYOUT BIT(2) + +/** + * enum exynos_cpuclk_layout - CPU clock registers layout compatibility + * @CPUCLK_LAYOUT_E4210: Exynos4210 compatible layout + * @CPUCLK_LAYOUT_E5433: Exynos5433 compatible layout + */ +enum exynos_cpuclk_layout { + CPUCLK_LAYOUT_E4210, + CPUCLK_LAYOUT_E5433, +}; /** * struct exynos_cpuclk_cfg_data - config data to setup cpu clocks diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index d1b72a75bc5a..bd017a68163d 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -773,7 +773,7 @@ static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = { static const struct samsung_cpu_clock exynos3250_cpu_clks[] __initconst = { CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C, - CLK_CPU_HAS_DIV1, 0x14000, e3250_armclk_d), + CLK_CPU_HAS_DIV1, 0x14000, CPUCLK_LAYOUT_E4210, e3250_armclk_d), }; static void __init exynos3_core_down_clock(void __iomem *reg_base) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 3d57020a620f..e1b7a5e0dbb8 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -1252,19 +1252,19 @@ static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = { static const struct samsung_cpu_clock exynos4210_cpu_clks[] __initconst = { CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_SCLK_MPLL, CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14000, - e4210_armclk_d), + CPUCLK_LAYOUT_E4210, e4210_armclk_d), }; static const struct samsung_cpu_clock exynos4212_cpu_clks[] __initconst = { CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C, CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14000, - e4212_armclk_d), + CPUCLK_LAYOUT_E4210, e4212_armclk_d), }; static const struct samsung_cpu_clock exynos4412_cpu_clks[] __initconst = { CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C, CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14000, - e4412_armclk_d), + CPUCLK_LAYOUT_E4210, e4412_armclk_d), }; /* register exynos4 clocks */ diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 4953da754994..36d28d466da9 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -776,7 +776,8 @@ static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = { static const struct samsung_cpu_clock exynos5250_cpu_clks[] __initconst = { CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL, - CLK_CPU_HAS_DIV1, 0x0, exynos5250_armclk_d), + CLK_CPU_HAS_DIV1, 0x0, CPUCLK_LAYOUT_E4210, + exynos5250_armclk_d), }; static const struct of_device_id ext_clk_match[] __initconst = { diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 531ef1c3fa30..f8cd28465b58 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1555,16 +1555,16 @@ static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = { static const struct samsung_cpu_clock exynos5420_cpu_clks[] __initconst = { CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0, - 0x0, exynos5420_eglclk_d), + 0x0, CPUCLK_LAYOUT_E4210, exynos5420_eglclk_d), CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0, - 0x28000, exynos5420_kfcclk_d), + 0x28000, CPUCLK_LAYOUT_E4210, exynos5420_kfcclk_d), }; static const struct samsung_cpu_clock exynos5800_cpu_clks[] __initconst = { CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0, - 0x0, exynos5800_eglclk_d), + 0x0, CPUCLK_LAYOUT_E4210, exynos5800_eglclk_d), CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0, - 0x28000, exynos5420_kfcclk_d), + 0x28000, CPUCLK_LAYOUT_E4210, exynos5420_kfcclk_d), }; static const struct of_device_id ext_clk_match[] __initconst = { diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 379744f0a5b6..d35901af21d0 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -3698,8 +3698,8 @@ static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst static const struct samsung_cpu_clock apollo_cpu_clks[] __initconst = { CPU_CLK(CLK_SCLK_APOLLO, "apolloclk", CLK_MOUT_APOLLO_PLL, - CLK_MOUT_BUS_PLL_APOLLO_USER, CLK_CPU_HAS_E5433_REGS_LAYOUT, - 0x0, exynos5433_apolloclk_d), + CLK_MOUT_BUS_PLL_APOLLO_USER, 0, 0x0, + CPUCLK_LAYOUT_E5433, exynos5433_apolloclk_d), }; static const struct samsung_cmu_info apollo_cmu_info __initconst = { @@ -3942,8 +3942,8 @@ static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = static const struct samsung_cpu_clock atlas_cpu_clks[] __initconst = { CPU_CLK(CLK_SCLK_ATLAS, "atlasclk", CLK_MOUT_ATLAS_PLL, - CLK_MOUT_BUS_PLL_ATLAS_USER, CLK_CPU_HAS_E5433_REGS_LAYOUT, - 0x0, exynos5433_atlasclk_d), + CLK_MOUT_BUS_PLL_ATLAS_USER, 0, 0x0, + CPUCLK_LAYOUT_E5433, exynos5433_atlasclk_d), }; static const struct samsung_cmu_info atlas_cmu_info __initconst = { diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index 8157479f45eb..87bbb8b31b03 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -283,10 +283,11 @@ struct samsung_cpu_clock { unsigned int alt_parent_id; unsigned long flags; int offset; + enum exynos_cpuclk_layout reg_layout; const struct exynos_cpuclk_cfg_data *cfg; }; -#define CPU_CLK(_id, _name, _pid, _apid, _flags, _offset, _cfg) \ +#define CPU_CLK(_id, _name, _pid, _apid, _flags, _offset, _layout, _cfg) \ { \ .id = _id, \ .name = _name, \ @@ -294,6 +295,7 @@ struct samsung_cpu_clock { .alt_parent_id = _apid, \ .flags = _flags, \ .offset = _offset, \ + .reg_layout = _layout, \ .cfg = _cfg, \ }