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Signed-off-by: Dingxian Wen Co-developed-by: Shreeya Patel Reviewed-by: Dmitry Osipenko Tested-by: Dmitry Osipenko Signed-off-by: Shreeya Patel --- .../boot/dts/rockchip/rk3588-pinctrl.dtsi | 41 +++++++++++++++ arch/arm64/boot/dts/rockchip/rk3588.dtsi | 50 +++++++++++++++++++ 2 files changed, 91 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi index 244c66faa161..4fbe194d96b1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi @@ -169,6 +169,47 @@ hdmim0_tx1_sda: hdmim0-tx1-sda { /* hdmim0_tx1_sda */ <2 RK_PB4 4 &pcfg_pull_none>; }; + + /omit-if-no-ref/ + hdmim1_rx: hdmim1-rx { + rockchip,pins = + /* hdmim1_rx_cec */ + <3 RK_PD1 5 &pcfg_pull_none>, + /* hdmim1_rx_scl */ + <3 RK_PD2 5 &pcfg_pull_none_smt>, + /* hdmim1_rx_sda */ + <3 RK_PD3 5 &pcfg_pull_none_smt>, + /* hdmim1_rx_hpdin */ + <3 RK_PD4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_rx_cec: hdmim1-rx-cec { + rockchip,pins = + /* hdmim1_rx_cec */ + <3 RK_PD1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_rx_hpdin: hdmim1-rx-hpdin { + rockchip,pins = + /* hdmim1_rx_hpdin */ + <3 RK_PD4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_rx_scl: hdmim1-rx-scl { + rockchip,pins = + /* hdmim1_rx_scl */ + <3 RK_PD2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_rx_sda: hdmim1-rx-sda { + rockchip,pins = + /* hdmim1_rx_sda */ + <3 RK_PD3 5 &pcfg_pull_none>; + }; }; i2c0 { diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index 5519c1430cb7..8138b6ee388f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -7,6 +7,24 @@ #include "rk3588-pinctrl.dtsi" / { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + /* + * The 4k HDMI capture controller works only with 32bit + * phys addresses and doesn't support IOMMU. HDMI RX CMA + * must be reserved below 4GB. + */ + hdmirx_cma: hdmirx_cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x0 0x0 0xffffffff>; + size = <0x0 (160 * 0x100000)>; /* 160MiB */ + no-map; + status = "disabled"; + }; + }; + pcie30_phy_grf: syscon@fd5b8000 { compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; reg = <0x0 0xfd5b8000 0x0 0x10000>; @@ -85,6 +103,38 @@ i2s10_8ch: i2s@fde00000 { status = "disabled"; }; + hdmirx_ctrler: hdmirx-controller@fdee0000 { + compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx"; + reg = <0x0 0xfdee0000 0x0 0x6000>; + power-domains = <&power RK3588_PD_VO1>; + rockchip,grf = <&sys_grf>; + rockchip,vo1_grf = <&vo1_grf>; + interrupts = , + , + ; + interrupt-names = "cec", "hdmi", "dma"; + clocks = <&cru ACLK_HDMIRX>, + <&cru CLK_HDMIRX_AUD>, + <&cru CLK_CR_PARA>, + <&cru PCLK_HDMIRX>, + <&cru CLK_HDMIRX_REF>, + <&cru PCLK_S_HDMIRX>, + <&cru HCLK_VO1>; + clock-names = "aclk", + "audio", + "cr_para", + "pclk", + "ref", + "hclk_s_hdmirx", + "hclk_vo1"; + resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>, + <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>; + reset-names = "rst_a", "rst_p", "rst_ref", "rst_biu"; + pinctrl-0 = <&hdmim1_rx>; + pinctrl-names = "default"; + status = "disabled"; + }; + pcie3x4: pcie@fe150000 { compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; #address-cells = <3>;