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Fri, 16 Feb 2024 10:51:10 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 4952022FA36; Fri, 16 Feb 2024 10:50:28 +0100 (CET) Received: from localhost (10.201.20.114) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 16 Feb 2024 10:50:27 +0100 From: Antonio Borneo To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon CC: Antonio Borneo , , , , Subject: [PATCH 11/12] arm64: dts: st: Add exti1 and exti2 nodes on stm32mp251 Date: Fri, 16 Feb 2024 10:47:56 +0100 Message-ID: <20240216094758.916722-12-antonio.borneo@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240216094758.916722-1-antonio.borneo@foss.st.com> References: <20240216094758.916722-1-antonio.borneo@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SAFCAS1NODE2.st.com (10.75.90.13) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-16_08,2024-02-14_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791049327904596166 X-GMAIL-MSGID: 1791049327904596166 Update the device-tree stm32mp251.dtsi by adding the nodes for exti1 and exti2 interrupt controllers. Signed-off-by: Antonio Borneo --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 140 +++++++++++++++++++++++++ 1 file changed, 140 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 5c9095382cc7..4253f5bcd000 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -164,6 +164,86 @@ package_otp@1e8 { }; }; + exti1: interrupt-controller@44220000 { + compatible = "st,stm32mp1-exti", "syscon"; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <0>; + reg = <0x44220000 0x400>; + + exti-interrupt-map { + #address-cells = <0>; + #interrupt-cells = <2>; + interrupt-map-mask = <0xffffffff 0>; + interrupt-map = + <0 0 &intc 0 0 GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &intc 0 0 GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &intc 0 0 GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &intc 0 0 GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &intc 0 0 GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &intc 0 0 GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &intc 0 0 GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &intc 0 0 GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, + <8 0 &intc 0 0 GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, + <9 0 &intc 0 0 GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, + <10 0 &intc 0 0 GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, + <11 0 &intc 0 0 GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <12 0 &intc 0 0 GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <13 0 &intc 0 0 GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <14 0 &intc 0 0 GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <15 0 &intc 0 0 GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <16 0 &intc 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <17 0 &intc 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <18 0 &intc 0 0 GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <19 0 &intc 0 0 GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, + <21 0 &intc 0 0 GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <22 0 &intc 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <23 0 &intc 0 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <24 0 &intc 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <25 0 &intc 0 0 GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <26 0 &intc 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <27 0 &intc 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <28 0 &intc 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <29 0 &intc 0 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <30 0 &intc 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <31 0 &intc 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <32 0 &intc 0 0 GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <33 0 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <34 0 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <36 0 &intc 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <37 0 &intc 0 0 GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <38 0 &intc 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <39 0 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <40 0 &intc 0 0 GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <41 0 &intc 0 0 GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <42 0 &intc 0 0 GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <43 0 &intc 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, + <44 0 &intc 0 0 GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <45 0 &intc 0 0 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, + <46 0 &intc 0 0 GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <47 0 &intc 0 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <48 0 &intc 0 0 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, + <49 0 &intc 0 0 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <50 0 &intc 0 0 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <59 0 &intc 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, + <61 0 &intc 0 0 GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, + <64 0 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <67 0 &intc 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <68 0 &intc 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <70 0 &intc 0 0 GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <72 0 &intc 0 0 GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, + <73 0 &intc 0 0 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <74 0 &intc 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <75 0 &intc 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <76 0 &intc 0 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <77 0 &intc 0 0 GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <78 0 &intc 0 0 GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <79 0 &intc 0 0 GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <83 0 &intc 0 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, + <84 0 &intc 0 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + syscfg: syscon@44230000 { compatible = "st,stm32mp25-syscfg", "syscon"; reg = <0x44230000 0x10000>; @@ -318,5 +398,65 @@ gpioz: gpio@46200000 { }; }; + + exti2: interrupt-controller@46230000 { + compatible = "st,stm32mp1-exti", "syscon"; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <0>; + reg = <0x46230000 0x400>; + + exti-interrupt-map { + #address-cells = <0>; + #interrupt-cells = <2>; + interrupt-map-mask = <0xffffffff 0>; + interrupt-map = + <0 0 &intc 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &intc 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &intc 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &intc 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &intc 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &intc 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &intc 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &intc 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <8 0 &intc 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <9 0 &intc 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <10 0 &intc 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <11 0 &intc 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <12 0 &intc 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <13 0 &intc 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <14 0 &intc 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <15 0 &intc 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <16 0 &intc 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <17 0 &intc 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <21 0 &intc 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <22 0 &intc 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <25 0 &intc 0 0 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <26 0 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <27 0 &intc 0 0 GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <29 0 &intc 0 0 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, + <30 0 &intc 0 0 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, + <31 0 &intc 0 0 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <33 0 &intc 0 0 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <34 0 &intc 0 0 GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, + <37 0 &intc 0 0 GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, + <40 0 &intc 0 0 GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, + <43 0 &intc 0 0 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <46 0 &intc 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <48 0 &intc 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <49 0 &intc 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <50 0 &intc 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <51 0 &intc 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <52 0 &intc 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <53 0 &intc 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <61 0 &intc 0 0 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, + <62 0 &intc 0 0 GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <64 0 &intc 0 0 GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <65 0 &intc 0 0 GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <66 0 &intc 0 0 GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, + <67 0 &intc 0 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <70 0 &intc 0 0 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; + }; + }; }; };