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AJvYcCWGzC6rqYo9+VAtpu0888D7EYqOU1R9db5FfdQi3C9DOs5aCKPccHL1rpjJVsC9heqx14ty500x5jp7uTsEumfxLhLvLFvdf4gG9K5X X-Gm-Message-State: AOJu0YxTqFkiy5Nr1WWDOgVHuS9EfeSNtmKdF+OJ3rKAbIWdknT5nsBg bQ7O4wM3FdUcfnro7cYVNYBHjrUe3O7JAW62zw7cN8oGefF8Wja6o0/SaKil7OI= X-Received: by 2002:a17:902:d48b:b0:1db:8181:9d04 with SMTP id c11-20020a170902d48b00b001db81819d04mr3724031plg.38.1708042127232; Thu, 15 Feb 2024 16:08:47 -0800 (PST) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id bb6-20020a170902bc8600b001db3d365082sm1789486plb.265.2024.02.15.16.08.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 16:08:45 -0800 (PST) From: Samuel Holland To: Will Deacon , Mark Rutland , Eric Lin , Conor Dooley Cc: Palmer Dabbelt , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Walmsley , linux-riscv@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, Samuel Holland Subject: [PATCH v1 3/6] dt-bindings: cache: Add SiFive Extensible Cache controller Date: Thu, 15 Feb 2024 16:08:15 -0800 Message-ID: <20240216000837.1868917-4-samuel.holland@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240216000837.1868917-1-samuel.holland@sifive.com> References: <20240216000837.1868917-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791012029091980405 X-GMAIL-MSGID: 1791012029091980405 From: Eric Lin Add YAML DT binding documentation for the SiFive Extensible Cache controller. The Extensible Cache controller interleaves cache blocks across a number of heterogeneous independently-programmed slices. Each slice contains an MMIO interface for configuration, cache maintenance, error reporting, and performance monitoring. Signed-off-by: Eric Lin Co-developed-by: Samuel Holland Signed-off-by: Samuel Holland --- .../cache/sifive,extensiblecache0.yaml | 136 ++++++++++++++++++ 1 file changed, 136 insertions(+) create mode 100644 Documentation/devicetree/bindings/cache/sifive,extensiblecache0.yaml diff --git a/Documentation/devicetree/bindings/cache/sifive,extensiblecache0.yaml b/Documentation/devicetree/bindings/cache/sifive,extensiblecache0.yaml new file mode 100644 index 000000000000..d027114dbdba --- /dev/null +++ b/Documentation/devicetree/bindings/cache/sifive,extensiblecache0.yaml @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2023-2024 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/sifive,extensiblecache0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive Extensible Cache Controller + +maintainers: + - Eric Lin + +description: + The SiFive Extensible Cache Controller provides a high-performance extensible + system (L2 or L3) cache. It is divided into several independent heterogeneous + slices, enabling a flexible topology and physical design. + +allOf: + - $ref: /schemas/cache-controller.yaml# + +select: + properties: + compatible: + contains: + enum: + - sifive,extensiblecache0 + + required: + - compatible + +properties: + compatible: + items: + - const: sifive,extensiblecache0 + - const: cache + + "#address-cells": true + "#size-cells": true + ranges: true + + interrupts: + maxItems: 1 + + cache-block-size: + const: 64 + + cache-level: true + cache-sets: true + cache-size: true + cache-unified: true + +patternProperties: + "^cache-controller@[0-9a-f]+$": + type: object + additionalProperties: false + properties: + reg: + maxItems: 1 + + cache-block-size: + const: 64 + + cache-sets: true + cache-size: true + cache-unified: true + + sifive,bm-event-counters: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + description: Number of bucket monitor registers in this slice + + sifive,cache-ways: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of ways in this slice (independent of cache size) + + sifive,perfmon-counters: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + description: Number of PMU counter registers in this slice + + required: + - reg + - cache-block-size + - cache-sets + - cache-size + - cache-unified + - sifive,cache-ways + +required: + - compatible + - ranges + - interrupts + - cache-block-size + - cache-level + - cache-sets + - cache-size + - cache-unified + +additionalProperties: false + +examples: + - | + cache-controller@30040000 { + compatible = "sifive,extensiblecache0", "cache"; + ranges = <0x30040000 0x30040000 0x10000>; + interrupts = <0x4>; + cache-block-size = <0x40>; + cache-level = <3>; + cache-sets = <0x800>; + cache-size = <0x100000>; + cache-unified; + #address-cells = <1>; + #size-cells = <1>; + + cache-controller@30040000 { + reg = <0x30040000 0x4000>; + cache-block-size = <0x40>; + cache-sets = <0x400>; + cache-size = <0x80000>; + cache-unified; + sifive,bm-event-counters = <8>; + sifive,cache-ways = <9>; + sifive,perfmon-counters = <8>; + }; + + cache-controller@30044000 { + reg = <0x30044000 0x4000>; + cache-block-size = <0x40>; + cache-sets = <0x400>; + cache-size = <0x80000>; + cache-unified; + sifive,bm-event-counters = <8>; + sifive,cache-ways = <9>; + sifive,perfmon-counters = <8>; + }; + };