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AJvYcCVRY1xF37tyTAHkTc+iAH2sDJrRgrJY7uMlDwGZyX63zIpXD1RO/10/iKmJfno8HCCS9XkVswxsBUdCEt3oCIdyTr74T1sQ34NAYag8ZHo2KXEhxhsYhimoxJ8xRsVtcxw++LJO8QOXXKcRtjGrTt33puC3iFmBBzFuJOQUalooZZmJ/CgJaA== X-Gm-Message-State: AOJu0YyzQyCYKzSA+dk2kOHUqVLM1CppO4E3/B5qJ/enHioeyrIzqehq A2mG4bLmxB0fW8o/J3LDsRiPpbfR/geBS3BRF4jZwb14USvLtNys X-Received: by 2002:a05:6512:1152:b0:511:7ebe:b160 with SMTP id m18-20020a056512115200b005117ebeb160mr2239460lfg.45.1708017472483; Thu, 15 Feb 2024 09:17:52 -0800 (PST) Received: from localhost ([178.176.56.174]) by smtp.gmail.com with ESMTPSA id p17-20020a19f011000000b005118f61ffb3sm309458lfc.233.2024.02.15.09.17.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 09:17:52 -0800 (PST) From: Serge Semin To: Thomas Bogendoerfer , Greg Kroah-Hartman , Jiri Slaby , Arnd Bergmann , Jiaxun Yang , Andrew Morton Cc: Serge Semin , Alexey Malahov , Stephen Rothwell , linux-mips@vger.kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] mips: cm: Add __mips_cm_l2sync_phys_base prototype declaration Date: Thu, 15 Feb 2024 20:17:26 +0300 Message-ID: <20240215171740.14550-2-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240215171740.14550-1-fancer.lancer@gmail.com> References: <20240215171740.14550-1-fancer.lancer@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790986162175737673 X-GMAIL-MSGID: 1790986162175737673 The __mips_cm_l2sync_phys_base() and mips_cm_l2sync_phys_base() couple was introduced in commit 9f98f3dd0c51 ("MIPS: Add generic CM probe & access code") where the former method was a weak implementation of the later function. Such design pattern permitted to re-define the original method and use the weak implementation in the new function. A similar approach was introduced in the framework of another arch-specific programmable interface: mips_cm_phys_base() and __mips_cm_phys_base(). The only difference is that the underscored method of the later couple was declared in the "asm/mips-cm.h" header file, but it wasn't done for the CM L2-sync methods in the subject. Due to the missing the global function declaration the "missing prototype" warning was spotted in the framework of the commit 9a2036724cd6 ("mips: mark local function static if possible") and fixed just be re-qualifying the weak method as static. Doing that broke what was originally implied by having the weak implementation globally defined. Fix that by dropping the static qualifier and adding the __mips_cm_l2sync_phys_base() prototype declared in the "asm/mips-cm.h" header file. Fixes: 9a2036724cd6 ("mips: mark local function static if possible") Signed-off-by: Serge Semin --- Note seeing there is no user of the pattern described above we can convert it to having just weakly defined methods. Let me know if that would be a better alternative. --- arch/mips/include/asm/mips-cm.h | 14 ++++++++++++++ arch/mips/kernel/mips-cm.c | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index 23c67c0871b1..1f143dfad7a2 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -33,6 +33,20 @@ extern void __iomem *mips_cm_l2sync_base; */ extern phys_addr_t __mips_cm_phys_base(void); +/** + * __mips_cm_l2sync_phys_base - retrieve the physical base address of the CM + * L2-sync region + * + * This function returns the physical base address of the Coherence Manager + * L2-cache only region. It provides a default implementation which reads the + * CMGCRL2OnlySyncBase register where available or returns a 4K region just + * behind the CM GCR base address. It may be overridden by platforms which + * determine this address in a different way by defining a function with the + * same prototype except for the name mips_cm_l2sync_phys_base (without + * underscores). + */ +extern phys_addr_t __mips_cm_l2sync_phys_base(void); + /* * mips_cm_is64 - determine CM register width * diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c index 84b3affb9de8..3f00788b0871 100644 --- a/arch/mips/kernel/mips-cm.c +++ b/arch/mips/kernel/mips-cm.c @@ -201,7 +201,7 @@ phys_addr_t __mips_cm_phys_base(void) phys_addr_t mips_cm_phys_base(void) __attribute__((weak, alias("__mips_cm_phys_base"))); -static phys_addr_t __mips_cm_l2sync_phys_base(void) +phys_addr_t __mips_cm_l2sync_phys_base(void) { u32 base_reg;