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bh=6rpcH0m9UcnLADJF2mMN2BFoCEixngqiqjxZKB2/Q2A=; b=KqAPq62K+Vl6Dnhks9nuocWaC08Kzifiv5oV1qkeJECqi+y0UkJK4OHy ZFrpyRnSxoCU0fKJd7rnPhV40JPRoO8LUf7PJ2gMdqxMmbKTehusfBaqF L+XExH6HxfV2UopcZJjWjO3a4e+9DIeY8xrXDJ9jdDF5Os5SHpj1KbZQT cIZqaves5vFq0vj51YQv8TyyzYaglCxP4d+JidEvtYjYUSD80nS2fV8Xr wwkmJ4qXgyGvJlYwLzflIYiRzQmay8+RFk7dOizvz4XhYFbhPOMj/ugNz sZGQtsDh5DKr3tkCYP0CikUOpHTRA005JFFR80uyXKdZZooAtOJigF933 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10984"; a="1943636" X-IronPort-AV: E=Sophos;i="6.06,161,1705392000"; d="scan'208";a="1943636" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2024 05:32:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,161,1705392000"; d="scan'208";a="26690910" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.246.32.150]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2024 05:32:35 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: Alex Deucher , amd-gfx@lists.freedesktop.org, Daniel Vetter , David Airlie , Dennis Dalessandro , dri-devel@lists.freedesktop.org, Jason Gunthorpe , Leon Romanovsky , linux-kernel@vger.kernel.org, linux-rdma@vger.kernel.org, "Pan, Xinhui" , =?utf-8?q?C?= =?utf-8?q?hristian_K=C3=B6nig?= Cc: =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Lukas Wunner , Dean Luick Subject: [PATCH 3/3] RDMA/hfi1: Use RMW accessors for changing LNKCTL2 Date: Thu, 15 Feb 2024 15:31:55 +0200 Message-Id: <20240215133155.9198-4-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240215133155.9198-1-ilpo.jarvinen@linux.intel.com> References: <20240215133155.9198-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790985637264820817 X-GMAIL-MSGID: 1790985637264820817 Convert open coded RMW accesses for LNKCTL2 to use pcie_capability_clear_and_set_word() which makes its easier to understand what the code tries to do. LNKCTL2 is not really owned by any driver because it is a collection of control bits that PCI core might need to touch. RMW accessors already have support for proper locking for a selected set of registers (LNKCTL2 is not yet among them but likely will be in the future) to avoid losing concurrent updates. Suggested-by: Lukas Wunner Signed-off-by: Ilpo Järvinen Reviewed-by: Dean Luick --- drivers/infiniband/hw/hfi1/pcie.c | 30 ++++++++---------------------- 1 file changed, 8 insertions(+), 22 deletions(-) diff --git a/drivers/infiniband/hw/hfi1/pcie.c b/drivers/infiniband/hw/hfi1/pcie.c index 119ec2f1382b..7133964749f8 100644 --- a/drivers/infiniband/hw/hfi1/pcie.c +++ b/drivers/infiniband/hw/hfi1/pcie.c @@ -1207,14 +1207,11 @@ int do_pcie_gen3_transition(struct hfi1_devdata *dd) (u32)lnkctl2); /* only write to parent if target is not as high as ours */ if ((lnkctl2 & PCI_EXP_LNKCTL2_TLS) < target_vector) { - lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS; - lnkctl2 |= target_vector; - dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, - (u32)lnkctl2); - ret = pcie_capability_write_word(parent, - PCI_EXP_LNKCTL2, lnkctl2); + ret = pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL2, + PCI_EXP_LNKCTL2_TLS, + target_vector); if (ret) { - dd_dev_err(dd, "Unable to write to PCI config\n"); + dd_dev_err(dd, "Unable to change parent PCI target speed\n"); return_error = 1; goto done; } @@ -1223,22 +1220,11 @@ int do_pcie_gen3_transition(struct hfi1_devdata *dd) } dd_dev_info(dd, "%s: setting target link speed\n", __func__); - ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL2, &lnkctl2); + ret = pcie_capability_clear_and_set_word(dd->pcidev, PCI_EXP_LNKCTL2, + PCI_EXP_LNKCTL2_TLS, + target_vector); if (ret) { - dd_dev_err(dd, "Unable to read from PCI config\n"); - return_error = 1; - goto done; - } - - dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, - (u32)lnkctl2); - lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS; - lnkctl2 |= target_vector; - dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, - (u32)lnkctl2); - ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL2, lnkctl2); - if (ret) { - dd_dev_err(dd, "Unable to write to PCI config\n"); + dd_dev_err(dd, "Unable to change device PCI target speed\n"); return_error = 1; goto done; }