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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF0002BA51.mail.protection.outlook.com (10.167.242.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7292.25 via Frontend Transport; Thu, 15 Feb 2024 11:32:56 +0000 Received: from gomati.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 15 Feb 2024 05:32:52 -0600 From: Nikunj A Dadhania To: , , , , CC: , , , , , , Subject: [PATCH v8 16/16] x86/sev: Enable Secure TSC for SNP guests Date: Thu, 15 Feb 2024 17:01:28 +0530 Message-ID: <20240215113128.275608-17-nikunj@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215113128.275608-1-nikunj@amd.com> References: <20240215113128.275608-1-nikunj@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA51:EE_|DS7PR12MB8417:EE_ X-MS-Office365-Filtering-Correlation-Id: e890a8be-b9c5-4b51-cd3b-08dc2e19db40 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Feb 2024 11:32:56.6660 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e890a8be-b9c5-4b51-cd3b-08dc2e19db40 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA51.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8417 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790965425695344259 X-GMAIL-MSGID: 1790965425695344259 Now that all the required plumbing is done for enabling SNP Secure TSC feature, add Secure TSC to snp features present list. Set the CPUID feature bit (X86_FEATURE_SNP_SECURE_TSC) when SNP guest is started with Secure TSC. Signed-off-by: Nikunj A Dadhania Tested-by: Peter Gonda --- arch/x86/boot/compressed/sev.c | 3 ++- arch/x86/mm/mem_encrypt.c | 10 ++++++++-- arch/x86/mm/mem_encrypt_amd.c | 4 +++- 3 files changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c index 073291832f44..d7e28084333a 100644 --- a/arch/x86/boot/compressed/sev.c +++ b/arch/x86/boot/compressed/sev.c @@ -379,7 +379,8 @@ static void enforce_vmpl0(void) * by the guest kernel. As and when a new feature is implemented in the * guest kernel, a corresponding bit should be added to the mask. */ -#define SNP_FEATURES_PRESENT MSR_AMD64_SNP_DEBUG_SWAP +#define SNP_FEATURES_PRESENT (MSR_AMD64_SNP_DEBUG_SWAP | \ + MSR_AMD64_SNP_SECURE_TSC) u64 snp_get_unsupported_features(u64 status) { diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c index 68aa06852466..350ba605509d 100644 --- a/arch/x86/mm/mem_encrypt.c +++ b/arch/x86/mm/mem_encrypt.c @@ -70,8 +70,14 @@ static void print_mem_encrypt_feature_info(void) pr_cont(" SEV-ES"); /* Secure Nested Paging */ - if (cc_platform_has(CC_ATTR_GUEST_SEV_SNP)) - pr_cont(" SEV-SNP"); + if (cc_platform_has(CC_ATTR_GUEST_SEV_SNP)) { + pr_cont(" SEV-SNP\n"); + pr_cont("SNP Features active: "); + + /* SNP Secure TSC */ + if (cpu_feature_enabled(X86_FEATURE_SNP_SECURE_TSC)) + pr_cont(" SECURE-TSC"); + } pr_cont("\n"); break; diff --git a/arch/x86/mm/mem_encrypt_amd.c b/arch/x86/mm/mem_encrypt_amd.c index cc936999efc8..7ee0a537a22e 100644 --- a/arch/x86/mm/mem_encrypt_amd.c +++ b/arch/x86/mm/mem_encrypt_amd.c @@ -500,8 +500,10 @@ void __init sme_early_init(void) ia32_disable(); /* Mark the TSC as reliable when Secure TSC is enabled */ - if (sev_status & MSR_AMD64_SNP_SECURE_TSC) + if (sev_status & MSR_AMD64_SNP_SECURE_TSC) { + setup_force_cpu_cap(X86_FEATURE_SNP_SECURE_TSC); setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); + } } void __init mem_encrypt_free_decrypted_mem(void)