diff mbox series

[v5,05/13] drm/mediatek: Set DRM mode configs accordingly

Message ID 20240215101119.12629-6-shawn.sung@mediatek.com
State New
Headers
Series Support IGT in display driver |

Commit Message

Shawn Sung (宋孝謙) Feb. 15, 2024, 10:11 a.m. UTC 
  Set DRM mode configs limitation according to the hardware capabilities
and pass the IGT checks as below:

- The test "graphics.IgtKms.kms_plane" requires a frame buffer with
  width of 4512 pixels (> 4096).
- The test "graphics.IgtKms.kms_cursor_crc" checks if the cursor size is
  defined, and run the test with cursor size from 1x1 to 512x512.

Please notice that the test conditions may change as IGT is updated.

Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 25 +++++++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_drv.h |  3 +++
 2 files changed, 28 insertions(+)

Comments

CK Hu (胡俊光) March 1, 2024, 7:21 a.m. UTC | #1 
Hi, Hsiao-chien:

On Thu, 2024-02-15 at 18:11 +0800, Hsiao Chien Sung wrote:
> Set DRM mode configs limitation according to the hardware
> capabilities
> and pass the IGT checks as below:
> 
> - The test "graphics.IgtKms.kms_plane" requires a frame buffer with
>   width of 4512 pixels (> 4096).
> - The test "graphics.IgtKms.kms_cursor_crc" checks if the cursor size
> is
>   defined, and run the test with cursor size from 1x1 to 512x512.
> 
> Please notice that the test conditions may change as IGT is updated.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c | 25
> +++++++++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_drm_drv.h |  3 +++
>  2 files changed, 28 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 890e1e93a2227..8cf157ec66ba6 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -296,6 +296,9 @@ static const struct mtk_mmsys_driver_data
> mt8188_vdosys0_driver_data = {
>  	.conn_routes = mt8188_mtk_ddp_main_routes,
>  	.num_conn_routes = ARRAY_SIZE(mt8188_mtk_ddp_main_routes),
>  	.mmsys_dev_num = 2,
> +	.max_pitch = GENMASK(15, 0),
> +	.min_width = 1,
> +	.min_height = 1,
>  };
>  
>  static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data =
> {
> @@ -310,6 +313,9 @@ static const struct mtk_mmsys_driver_data
> mt8195_vdosys0_driver_data = {
>  	.main_path = mt8195_mtk_ddp_main,
>  	.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
>  	.mmsys_dev_num = 2,
> +	.max_pitch = GENMASK(15, 0),
> +	.min_width = 1,
> +	.min_height = 1,
>  };
>  
>  static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data
> = {
> @@ -317,6 +323,9 @@ static const struct mtk_mmsys_driver_data
> mt8195_vdosys1_driver_data = {
>  	.ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
>  	.mmsys_id = 1,
>  	.mmsys_dev_num = 2,
> +	.max_pitch = GENMASK(15, 0),
> +	.min_width = 2, /* 2-pixel align when ethdr is bypassed */
> +	.min_height = 1,
>  };
>  
>  static const struct of_device_id mtk_drm_of_ids[] = {
> @@ -495,6 +504,18 @@ static int mtk_drm_kms_init(struct drm_device
> *drm)
>  		for (j = 0; j < private->data->mmsys_dev_num; j++) {
>  			priv_n = private->all_drm_private[j];
>  
> +			if (priv_n->data->max_pitch) {
> +				/* Save 4 bytes for the color depth
> (pitch = width * bpp) */
> +				drm->mode_config.max_width  = priv_n-
> >data->max_pitch >> 2;
> +				drm->mode_config.max_height = priv_n-
> >data->max_pitch >> 2;

I think the term 'pitch' is for width not for height. And I think you
should not divide height by 4. So I would like to have priv_n->data-
>max_height.

Regards,
CK

> +			}
> +
> +			if (priv_n->data->min_width)
> +				drm->mode_config.min_width = priv_n-
> >data->min_width;
> +
> +			if (priv_n->data->min_height)
> +				drm->mode_config.min_height = priv_n-
> >data->min_height;
> +
>  			if (i == CRTC_MAIN && priv_n->data->main_len) {
>  				ret = mtk_drm_crtc_create(drm, priv_n-
> >data->main_path,
>  							  priv_n->data-
> >main_len, j,
> @@ -522,6 +543,10 @@ static int mtk_drm_kms_init(struct drm_device
> *drm)
>  		}
>  	}
>  
> +	/* IGT will check if the cursor size is configured */
> +	drm->mode_config.cursor_width = drm->mode_config.max_width;
> +	drm->mode_config.cursor_height = drm->mode_config.max_height;
> +
>  	/* Use OVL device for all DMA memory allocations */
>  	crtc = drm_crtc_from_index(drm, 0);
>  	if (crtc)
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index 33fadb08dc1c7..414764b4546ba 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -46,6 +46,9 @@ struct mtk_mmsys_driver_data {
>  	bool shadow_register;
>  	unsigned int mmsys_id;
>  	unsigned int mmsys_dev_num;
> +
> +	u32 max_pitch;
> +	int min_width, min_height;
>  };
>  
>  struct mtk_drm_private {
diff mbox series

Patch

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 890e1e93a2227..8cf157ec66ba6 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -296,6 +296,9 @@  static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
 	.conn_routes = mt8188_mtk_ddp_main_routes,
 	.num_conn_routes = ARRAY_SIZE(mt8188_mtk_ddp_main_routes),
 	.mmsys_dev_num = 2,
+	.max_pitch = GENMASK(15, 0),
+	.min_width = 1,
+	.min_height = 1,
 };
 
 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
@@ -310,6 +313,9 @@  static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
 	.main_path = mt8195_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
 	.mmsys_dev_num = 2,
+	.max_pitch = GENMASK(15, 0),
+	.min_width = 1,
+	.min_height = 1,
 };
 
 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
@@ -317,6 +323,9 @@  static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
 	.mmsys_id = 1,
 	.mmsys_dev_num = 2,
+	.max_pitch = GENMASK(15, 0),
+	.min_width = 2, /* 2-pixel align when ethdr is bypassed */
+	.min_height = 1,
 };
 
 static const struct of_device_id mtk_drm_of_ids[] = {
@@ -495,6 +504,18 @@  static int mtk_drm_kms_init(struct drm_device *drm)
 		for (j = 0; j < private->data->mmsys_dev_num; j++) {
 			priv_n = private->all_drm_private[j];
 
+			if (priv_n->data->max_pitch) {
+				/* Save 4 bytes for the color depth (pitch = width * bpp) */
+				drm->mode_config.max_width  = priv_n->data->max_pitch >> 2;
+				drm->mode_config.max_height = priv_n->data->max_pitch >> 2;
+			}
+
+			if (priv_n->data->min_width)
+				drm->mode_config.min_width = priv_n->data->min_width;
+
+			if (priv_n->data->min_height)
+				drm->mode_config.min_height = priv_n->data->min_height;
+
 			if (i == CRTC_MAIN && priv_n->data->main_len) {
 				ret = mtk_drm_crtc_create(drm, priv_n->data->main_path,
 							  priv_n->data->main_len, j,
@@ -522,6 +543,10 @@  static int mtk_drm_kms_init(struct drm_device *drm)
 		}
 	}
 
+	/* IGT will check if the cursor size is configured */
+	drm->mode_config.cursor_width = drm->mode_config.max_width;
+	drm->mode_config.cursor_height = drm->mode_config.max_height;
+
 	/* Use OVL device for all DMA memory allocations */
 	crtc = drm_crtc_from_index(drm, 0);
 	if (crtc)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 33fadb08dc1c7..414764b4546ba 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -46,6 +46,9 @@  struct mtk_mmsys_driver_data {
 	bool shadow_register;
 	unsigned int mmsys_id;
 	unsigned int mmsys_dev_num;
+
+	u32 max_pitch;
+	int min_width, min_height;
 };
 
 struct mtk_drm_private {