diff mbox series

Revert "drm/panel-edp: Add auo_b116xa3_mode"

Message ID 20240214072435.1496536-2-hsinyi@chromium.org
State New
Headers
Series Revert "drm/panel-edp: Add auo_b116xa3_mode" |

Commit Message

Hsin-Yi Wang Feb. 14, 2024, 7:22 a.m. UTC 
  This reverts commit 70e0d5550f5cec301ad116703b840a539fe985dc.

The overridden mode fixes the panel glitching issue on mt8186 chromebook.
However, it causes the internal display not working on mt8173 chromebook.
Revert the overridden mode for now to let mt8173 have a functional display.

Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
---
 drivers/gpu/drm/panel/panel-edp.c | 19 ++-----------------
 1 file changed, 2 insertions(+), 17 deletions(-)

Comments

Doug Anderson Feb. 14, 2024, 9:41 p.m. UTC | #1 
Hi,

On Tue, Feb 13, 2024 at 11:24 PM Hsin-Yi Wang <hsinyi@chromium.org> wrote:
>
> This reverts commit 70e0d5550f5cec301ad116703b840a539fe985dc.
>
> The overridden mode fixes the panel glitching issue on mt8186 chromebook.
> However, it causes the internal display not working on mt8173 chromebook.
> Revert the overridden mode for now to let mt8173 have a functional display.
>
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> ---
>  drivers/gpu/drm/panel/panel-edp.c | 19 ++-----------------
>  1 file changed, 2 insertions(+), 17 deletions(-)

Given that the breakage for affected mt8173 Chromebooks is pretty bad
(black screen), I'll plan to just wait an extra day for any screams
and then I'll apply to drm-misc-fixes.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Doug Anderson Feb. 15, 2024, 4:36 p.m. UTC | #2 
Hi,

On Wed, Feb 14, 2024 at 1:41 PM Doug Anderson <dianders@chromium.org> wrote:
>
> Hi,
>
> On Tue, Feb 13, 2024 at 11:24 PM Hsin-Yi Wang <hsinyi@chromium.org> wrote:
> >
> > This reverts commit 70e0d5550f5cec301ad116703b840a539fe985dc.
> >
> > The overridden mode fixes the panel glitching issue on mt8186 chromebook.
> > However, it causes the internal display not working on mt8173 chromebook.
> > Revert the overridden mode for now to let mt8173 have a functional display.
> >
> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> > ---
> >  drivers/gpu/drm/panel/panel-edp.c | 19 ++-----------------
> >  1 file changed, 2 insertions(+), 17 deletions(-)
>
> Given that the breakage for affected mt8173 Chromebooks is pretty bad
> (black screen), I'll plan to just wait an extra day for any screams
> and then I'll apply to drm-misc-fixes.
>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>

It caused a merge conflict against drm-misc-fixes since other panels
have been added in the meantime. I'm going to stick this in
drm-misc-next to avoid the merge headache. If someone is affected and
really wants this in fixes, please shout and we can figure out how to
make it happen.

1a5e81de180e Revert "drm/panel-edp: Add auo_b116xa3_mode"

-Doug
diff mbox series

Patch

diff --git a/drivers/gpu/drm/panel/panel-edp.c b/drivers/gpu/drm/panel/panel-edp.c
index 7d556b1bfa82..bd71d239272a 100644
--- a/drivers/gpu/drm/panel/panel-edp.c
+++ b/drivers/gpu/drm/panel/panel-edp.c
@@ -1002,19 +1002,6 @@  static const struct panel_desc auo_b101ean01 = {
 	},
 };
 
-static const struct drm_display_mode auo_b116xa3_mode = {
-	.clock = 70589,
-	.hdisplay = 1366,
-	.hsync_start = 1366 + 40,
-	.hsync_end = 1366 + 40 + 40,
-	.htotal = 1366 + 40 + 40 + 32,
-	.vdisplay = 768,
-	.vsync_start = 768 + 10,
-	.vsync_end = 768 + 10 + 12,
-	.vtotal = 768 + 10 + 12 + 6,
-	.flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
-};
-
 static const struct drm_display_mode auo_b116xak01_mode = {
 	.clock = 69300,
 	.hdisplay = 1366,
@@ -1963,12 +1950,10 @@  static const struct edp_panel_entry edp_panels[] = {
 	EDP_PANEL_ENTRY('A', 'U', 'O', 0x239b, &delay_200_500_e50, "B116XAN06.1"),
 	EDP_PANEL_ENTRY('A', 'U', 'O', 0x255c, &delay_200_500_e50, "B116XTN02.5"),
 	EDP_PANEL_ENTRY('A', 'U', 'O', 0x403d, &delay_200_500_e50, "B140HAN04.0"),
-	EDP_PANEL_ENTRY2('A', 'U', 'O', 0x405c, &auo_b116xak01.delay, "B116XAK01.0",
-			 &auo_b116xa3_mode),
+	EDP_PANEL_ENTRY('A', 'U', 'O', 0x405c, &auo_b116xak01.delay, "B116XAK01.0"),
 	EDP_PANEL_ENTRY('A', 'U', 'O', 0x435c, &delay_200_500_e50, "Unknown"),
 	EDP_PANEL_ENTRY('A', 'U', 'O', 0x582d, &delay_200_500_e50, "B133UAN01.0"),
-	EDP_PANEL_ENTRY2('A', 'U', 'O', 0x615c, &delay_200_500_e50, "B116XAN06.1",
-			 &auo_b116xa3_mode),
+	EDP_PANEL_ENTRY('A', 'U', 'O', 0x615c, &delay_200_500_e50, "B116XAN06.1"),
 	EDP_PANEL_ENTRY('A', 'U', 'O', 0x635c, &delay_200_500_e50, "B116XAN06.3"),
 	EDP_PANEL_ENTRY('A', 'U', 'O', 0x639c, &delay_200_500_e50, "B140HAK02.7"),
 	EDP_PANEL_ENTRY('A', 'U', 'O', 0x723c, &delay_200_500_e50, "B140XTN07.2"),