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h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=gIoofpF9d/n7cxls2/M/6yTKRz9FD7GPyY2q7V+P96rziAExt+wGu6uKRnJ9zPGTT Ubb0HXR9I6YH2Wg7WRDUawLcmToqviGXswwtJlu9LshceVzIwUMa4sizQWKOYaXxqy S3GI/DMBAxPZe/lW4bsiRtPKUt4ymyJ4/zsWUTnZ3iIzvCQ+vxaaVLed3TqIjcfJrT pC0O36kJbdlaejMoTK7wbie9P1MGtZuPHT1HLoeAdxW8rgUmQroVk7siair8IHlFJr XSCNj/2fc97l8Xej1dRncmZ77+fIJh8YmZRzFeXjPqFQSK4DPewNVugswejXwptxBI yk8SoHBlHw8uQ== Received: from localhost (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by madrid.collaboradmins.com (Postfix) with ESMTPSA id DF80F378207B; Wed, 14 Feb 2024 11:46:38 +0000 (UTC) From: Cristian Ciocaltea Date: Wed, 14 Feb 2024 13:45:36 +0200 Subject: [PATCH v4 1/2] dt-bindings: phy: Add Rockchip HDMI/eDP Combo PHY schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240214-phy-hdptx-v4-1-e7974f46c1a7@collabora.com> References: <20240214-phy-hdptx-v4-0-e7974f46c1a7@collabora.com> In-Reply-To: <20240214-phy-hdptx-v4-0-e7974f46c1a7@collabora.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Johan Jonker , Sebastian Reichel , Sascha Hauer , Andy Yan , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Algea Cao Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, kernel@collabora.com, Krzysztof Kozlowski X-Mailer: b4 0.13-dev-a684c X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790874736145344317 X-GMAIL-MSGID: 1790874736145344317 Add dt-binding schema for the HDMI/eDP Transmitter Combo PHY found on Rockchip RK3588 SoC. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Heiko Stuebner Signed-off-by: Cristian Ciocaltea --- .../bindings/phy/rockchip,rk3588-hdptx-phy.yaml | 91 ++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml new file mode 100644 index 000000000000..54e822c715f3 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip,rk3588-hdptx-phy.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,rk3588-hdptx-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip SoC HDMI/eDP Transmitter Combo PHY + +maintainers: + - Cristian Ciocaltea + +properties: + compatible: + enum: + - rockchip,rk3588-hdptx-phy + + reg: + maxItems: 1 + + clocks: + items: + - description: Reference clock + - description: APB clock + + clock-names: + items: + - const: ref + - const: apb + + "#phy-cells": + const: 0 + + resets: + items: + - description: PHY reset line + - description: APB reset line + - description: INIT reset line + - description: CMN reset line + - description: LANE reset line + - description: ROPLL reset line + - description: LCPLL reset line + + reset-names: + items: + - const: phy + - const: apb + - const: init + - const: cmn + - const: lane + - const: ropll + - const: lcpll + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: Some PHY related data is accessed through GRF regs. + +required: + - compatible + - reg + - clocks + - clock-names + - "#phy-cells" + - resets + - reset-names + - rockchip,grf + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + phy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0xfed60000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; + clock-names = "ref", "apb"; + #phy-cells = <0>; + resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, + <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, + <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, + <&cru SRST_HDPTX0_LCPLL>; + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", "lcpll"; + rockchip,grf = <&hdptxphy_grf>; + }; + };